View ZL50407_291268.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZL50407 Lightly Managed/Unmanaged 8FE + 1GE Layer-2 Ethernet Switch
Data Sheet Zarlink Features
* Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch * Eight 10/100 Mbps auto-negotiating Fast Ethernet (FE) ports with RMII, MII, GPSI, Reverse MII & Reverse GPSI interface options * One 10/100/1000 Mbps auto-negotiating port with GMII & MII interface options, that can be used as a WAN uplink or as a 9th port Embedded 2.0 Mbits (256 KBytes) internal memory for control databases and frame data buffer * Supports jumbo frames up to 4 KBytes CPU access supports the following interface options: * Serial interface in lightly managed mode, or in unmanaged mode with optional I2C EEPROM interface Operates stand-alone or can be cascaded with a second ZL50407 to reach 16 ports Ethernet IEEE 802.3x flow control for full duplex ports, back pressure flow control for half duplex ports Built-in reset logic triggered by system malfunction Built-In Self Test for internal SRAM Ordering Information ZL50407GDC ZL50407GDG2 208-Ball LBGA 208-Ball LBGA**
April 2006
**Pb Free Tin/Silver/Copper -40C to +85C * IEEE-1149.1 (JTAG) test port
*
L2 Switching
* L2 switching * MAC address self learning, up to 4 K MAC addresses * MAC address table supports unicast MAC address learning Supports the following spanning standards * IEEE 802.1D spanning tree * IEEE 802.1w rapid spanning tree Supports Ethernet multicasting and broadcasting and flooding control
*
* *
*
*
* *
C P U
Serial
ZL50407
GMII / MII
8-Port 10/100M + 1G Ethernet Switch
EEPROM
I2C
10/100/ 1000 PHY
RMII / MII / GPSI
Quad 10/100 PHY
Quad 10/100 PHY
Figure 1 - System Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50407 VLAN Support Features
* Supports the following VLAN standards * port-based VLAN
Data Sheet
Classification and Security
* Search engine classification * Classifies packets based on single field - Source and destination L4 logical ports, or - TOS/DS, or - VLAN (IEEE 802.1p), or - Physical port * Assigns a transmission priority and drop precedence Packet filtering and security * Static address filtering for source and/or destination MAC addresses * Static MAC address not subject to aging * Secure mode freezes MAC address learning (each port may independently use this mode) * IEEE 802.1x access control * Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of port VLAN ID
*
Traffic Management
* * * * Two (2) transmission classes for FE ports and four (4) transmission classes for uplink port Scheduling using weighted fair queuing (WFQ) or strict priority (SP) discipline At egress, per-queue weighted random early discard (WRED) with 2 drop precedence levels * Configurable WRED thresholds For FE ports, supports ingress and egress rate control * Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement) * Granularity of rate regulation to 16 Kbps * Ingress rate regulated using WRED, with 2 drop precedence levels, or flow control Output traffic regulation per class available on uplink port Fully supports Differentiated Services' Expedited and Assured Forwarding (EF and AF) per-hop behaviours Intelligent buffer management * Achieves high buffer utilization while ensuring fairness among traffic classes and ports * Buffer reservations per class and per source port Failover Features * Rapid link failure detection using hardware-generated heartbeat packets * link failover in less than 50 ms Supports concentration mode Supports IEEE 802.3ad link aggregation * Eight (8) groups of up to 8 ports per group * Allows trunking of ports located on cascaded chip * Supports load sharing among trunk ports based on: - Source port - Source and/or destination MAC address Traffic Mirroring * Physical port based (RMII enabled ports only) * Source or destination MAC address based * MAC address pair based Supports module hot swap on all ports
* * *
*
* *
*
*
2
Zarlink Semiconductor Inc.
ZL50407 Network Management Support
* Built-in RMON MIB counters
Data Sheet
Description
The ZL50407 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100/1000 Mbps, and a CPU interface for lightly managed and unmanaged switch applications. The chip supports up to 4 K MAC addresses and port-based Virtual LANs (VLANs). With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50407 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50407 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50407 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. The ZL50407 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50407 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50407 is fabricated using 0.18 micron technology. The ZL50407 is packaged in a 208-pin Ball Grid Array package.
3
Zarlink Semiconductor Inc.
ZL50407 Changes Summary
July 2003 * Initial Release
Data Sheet
November 2003 * Updated Ball Signal Description Table (1.3, "Ball Signal Descriptions" on page 14): * clarified the ball signal I/O description for Mn_TXCLK & Mn_RXCLK showing these signals are either inputs OR outputs * clarified that M9_MTXCLK is an input only Updated 1.4, "Signal Mapping and Internal pull-up/Down Configuration" on page 19 to indicate operation of the internal pull-up/down resistors in different modes Clarified 10.1.3, "GMAC Reference Clock (GREF_CLK) Speed Requirement" on page 46 on usage of GREF_CLK Clarified PVMODE register bit description for bits [2] & [5] Updated ECR4Pn register description as port 9 (uplink) operates differently than the RMAC ports for MII bi-directional clocking (bits [1:0]) I2C address mapping was corrected for QOSCn registers Added Maximum Junction Temperature to 13.1, "Absolute Maximum Ratings" on page 118 Updated I/O voltage levels to use TTL spec values rather than % of Vcc (13.2, "DC Electrical Characteristics" on page 118)
* * * * * * *
February 2004 * Added the following to the Feature List: * 4 K jumbo frames * IEEE 802.3ad support * Reverse MII/GPSI Added section on PHY addresses (2.2.4, "PHY Addresses" on page 25) * Clarified that they are hard-coded Fixed error in DS on sending Ethernet Frames via serial interface. * The Status Bytes is sent before the frame, for both Tx and Rx Added more cross-references to available AppNotes Added more clock descriptions to 10.0, "Clocks" on page 46 INT_MASK and INTP_MASK registers should state that the default register value is 0x00
* * * * *
August 2004 * * * Added section Changes Summary to document Added section on SCL clock generation (10.2.2, "SCL" on page 46) Interrupt Register was incorrectly identified as read only, should be read/write * Clarified that only bit [7] is not self-clearing
November 2004 * Added section 1.6, "Default Switch Configuration and Initialization Sequence" on page 22
January 2005 * Updated GMII timing (13.4.9, "Gigabit Media Independent Interface (GMII)" on page 128) * reduce min. hold time from 1ns to 0.5ns * reduced max. output delay by 1ns Removed reference to direct register INDEX_REG1 (address 0x1) from SSI diagrams, as not applicable
*
4
Zarlink Semiconductor Inc.
ZL50407
June 2005 * * * * * *
Data Sheet
Clarified that port mirroring is only available if the source & destination ports are in RMII mode Updated PVMODE bit [5] to reflect the proper MAC address range: 01-80-C2-00-00-00~F Clarified DATAOUT output can be open-drain or totem-pole based on debounce selection via bootstrap TSTOUT[0] Added power sequencing recommendation (1.7, "Power Sequencing" on page 23) Added Reverse MII/GPSI timing characteristics (13.4.8, "Reverse General Purpose Serial Interface (RvGPSI)" on page 127 and 13.4.10, "MII Management Data Interface (MDIO/MDC)" on page 130) Clarified that counter "DelayExceededDiscards" is not applicable for the ZL50407 (11.0, "Hardware Statistics Counters" on page 47)
December 2005 * * * * Clarified that TRST signal should be externally tied to GND via weak resistor, as per JTAG standard (1.3, "Ball Signal Descriptions" on page 14) Added more text to section 2.8, "JTAG" on page 26 Clarified counter definitions (11.0, "Hardware Statistics Counters" on page 47) Removed definition for SE_OPMODE bit[5] (ARP report control), as this feature was not implemented and this bit was mistakenly left in the register definition.
April 2006 * * * * Added Pb-free order code (ZL50407GDG2) Removed mention of multicast MAC address learning support, as feature is not available on the unmanaged/lightly managed chipsets Clarified registers UCC, MCC & MCCTH Renamed register UCC (now PCC), as name was misleading
5
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 November 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 January 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 June 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 December 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 April 2006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 Power and Ground Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 Ball Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 Signal Mapping and Internal pull-up/Down Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.1 Recommended Default Bootstrap Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6 Default Switch Configuration and Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2 MAC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1.1 GPSI (7WS) Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.2 CPU MAC Module (CMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.3 GMII MAC Module (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.4 PHY Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.6 Heartbeat Packet Generation and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.7 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8.2 Test Access Port (TAP) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.8.3 Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.0 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1 Register Configuration, Frame Transmission and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
4.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 Search, Learning and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 MAC Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.8 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.9 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.6 TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 Two QoS Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.1 Strict Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.2 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.5 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.6 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7 Flow Control Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.8 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9 Failover Backplane Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.0 Traffic Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 Using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.0 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.1 System Clock (SCLK) Speed Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.2 RMAC Reference Clock (M_CLK) Speed Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.1.3 GMAC Reference Clock (GREF_CLK) Speed Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
10.1.4 JTAG Test Clock (TCK) Speed Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2 Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2.3 Ethernet Interface Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2 IEEE 802.3 HUB Management (RFC 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1.1 PortReadableFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1.2 PortReadableOctets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1.3 PortFCSErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2.1.4 PortAlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2.1.5 PortFrameTooLongs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2.1.6 PortShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2.1.7 PortRunts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2.1.8 PortCollisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.9 PortLateEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.10 PortVeryLongEvents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.11 PortDataRateMisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.12 PortAutoPartitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.13 PortTotalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.3 IEEE 802.1 Bridge Management (RFC 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3.1.1 PortDelayExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3.1.2 PortMtuExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3.1.3 PortInFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3.1.4 PortOutFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3.1.5 PortInDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4 RMON - Ethernet Statistic Group (RFC 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4.1.1 DropEvents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4.1.2 Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4.1.3 Pkts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.4.1.4 BroadcastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.4.1.5 MulticastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.4.1.6 CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.4.1.7 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1.8 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1.9 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1.10 Jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.11 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.12 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 ZL50407 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.3 Indirectly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3.1 (Group 0 Address) MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3.1.1 ECR1Pn: Port n Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3.1.2 ECR2Pn: Port n Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3.1.3 ECR3Pn: Port n Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
12.3.1.4 ECR4Pn: Port n Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.3.1.5 BUF_LIMIT - Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.1.6 FCC - Flow Control Grant Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.1 AVTCL - VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.2 AVTCH - VLAN Type Code Register High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.3 PVMAP00_0 - Port 0 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3.2.4 PVMAP00_1 - Port 0 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3.2.5 PVMAP00_3 - Port 0 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3.2.6 PVMAPnn_0,1,3 - Ports 1~9 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.3.2.7 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.3.3 (Group 2 Address) Port Trunking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.3.3.1 TRUNKn- Trunk Group 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.3.3.2 TRUNKn_HASH10 - Trunk group n hash result 1/0 destination port number . . . . . . . . . . . 75 12.3.3.3 TRUNKn_HASH32 - Trunk group n hash result 3/2 destination port number . . . . . . . . . . . 75 12.3.3.4 TRUNKn_HASH54 - Trunk group n hash result 5/4 destination port number . . . . . . . . . . . 76 12.3.3.5 TRUNKn_HASH76 - Trunk group n hash result 7/6 destination port number . . . . . . . . . . . 76 Multicast Hash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.3.3.6 MULTICAST_HASHn-0 - Multicast hash result 0~7 mask byte 0 . . . . . . . . . . . . . . . . . . . . 77 12.3.3.7 MULTICAST_HASHn-1 - Multicast hash result 0~7 mask byte 1 . . . . . . . . . . . . . . . . . . . . 77 12.3.4 (Group 3 Address) CPU Port Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.1 MAC0 - CPU MAC address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.2 MAC1 - CPU MAC address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.3 MAC2 - CPU MAC address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.4 MAC3 - CPU MAC address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.5 MAC4 - CPU MAC address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.6 MAC5 - CPU MAC address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.7 INT_MASK0 - Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.8 INTP_MASK0 - Interrupt Mask for MAC Port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.3.4.9 INTP_MASKn - Interrupt Mask for MAC Ports 2~9 Registers . . . . . . . . . . . . . . . . . . . . . . . 79 12.3.4.10 RQS - Receive Queue Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.11 RQSS - Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.12 MAC01 - Increment MAC port 0,1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.13 MAC23 - Increment MAC port 2,3 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.4.14 MAC45 - Increment MAC port 4,5 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.4.15 MAC67 - Increment MAC port 6,7 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.4.16 MAC9 - Increment MAC port 9 address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.4.17 CPUQINS0 - CPUQINS6 - CPU Queue Insertion Command . . . . . . . . . . . . . . . . . . . . . . 82 12.3.4.18 CPUQINSRPT - CPU Queue Insertion Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 - CPU Allocated Granule Pointer . . . . . . . . . . . . . . . . . 83 12.3.4.20 CPURLSINFO0 - CPURLSINFO4 - Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.4.21 CPUGRNCTR - CPU Granule Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.5 (Group 4 Address) Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.5.1 AGETIME_LOW - MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.5.2 AGETIME_HIGH -MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.5.3 SE_OPMODE - Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.6 (Group 5 Address) Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.1 QOSC - QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.2 PCC - Packet Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.3 MCC - Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.4 MCCTH - Multicast Threshold Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.6.5 RDRC0 - WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
12.3.6.6 RDRC1 - WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.6.7 RDRC2 - WRED Rate Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.6.8 SFCB - Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.6.9 C1RS - Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.6.10 C2RS - Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.6.11 C3RS - Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.6.12 AVPML - VLAN Tag Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.6.13 AVPMM - VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.6.14 AVPMH - VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.3.6.15 AVDM - VLAN Discard Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.3.6.16 TOSPML - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.3.6.17 TOSPMM - TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3.6.18 TOSPMH - TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3.6.19 TOSDML - TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3.6.20 USER_PROTOCOL_n - User Define Protocol 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.3.6.21 USER_PROTOCOL_FORCE_DISCARD - User Define Protocol 0~7 Force Discard . . . . 91 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.3.6.22 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . 92 12.3.6.23 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . 92 12.3.6.24 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . 93 12.3.6.25 WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . . 93 12.3.6.26 WELL_KNOWN_PORT_ENABLE - Well Known Logic Port 0 to 7 Enables . . . . . . . . . . . 93 12.3.6.27 WELL_KNOWN_PORT_FORCE_DISCARD - Well Known Logic Port 0~7 Force Discard93 12.3.6.28 USER_PORT[7:0]_[LOW/HIGH] - User Define Logical Port 0~7 . . . . . . . . . . . . . . . . . . . 94 12.3.6.29 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . . . . 94 12.3.6.30 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . . . . 95 12.3.6.31 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . . . . 95 12.3.6.32 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . . . . 95 12.3.6.33 USER_PORT_ENABLE[7:0] - User Define Logic Port 0 to 7 Enables . . . . . . . . . . . . . . . 95 12.3.6.34 USER_PORT_FORCE_DISCARD[7:0] - User Define Logic Port 0~7 Force Discard . . . . 96 12.3.6.35 RLOWL - User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.6.36 RLOWH - User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.6.37 RHIGHL - User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.6.38 RHIGHH - User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.6.39 RPRIORITY - User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7 (Group 6 Address) MISC Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7.1 MII_OP0 - MII Register Option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7.2 MII_OP1 - MII Register Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3.7.3 FEN - Feature Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3.7.4 MIIC0 - MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.5 MIIC1 - MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.6 MIIC2 - MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.7 MIIC3 - MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.8 MIID0 - MII Data Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.7.9 MIID1 - MII Data Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.7.10 USD - One Micro Second Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.7.11 DEVICE - Device Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.7.12 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.7.13 LHBTimer - Link Heart Beat Timeout Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.7.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.7.15 fMACCReg0, fMACCReg1 - MAC Control Frame OpCode . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.7.16 FCB Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
12.3.7.17 FCB Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.7.18 FCB Base Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.8 (Group 7 Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.8.1 MIRROR CONTROL - Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.8.2 MIRROR_DEST_MAC[5:0] - Mirror Destination MAC Address 0~5 . . . . . . . . . . . . . . . . . 102 12.3.8.3 MIRROR_SRC _MAC[5:0] - Mirror Source MAC Address 0~5 . . . . . . . . . . . . . . . . . . . . . 102 12.3.8.4 RMII_MIRROR0 - RMII Mirror 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.8.5 RMII_MIRROR1 - RMII Mirror 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9 (Group 8 Address) Per Port QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9.1 FCRn - Port 0~9 Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.9.3 PR100_n - Port 0~7 Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.9.4 PR100_CPU - Port CPU Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.9.5 PRG - Port GMAC Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.9.6 PTH100_n - Port 0~7 Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.9.7 PTH100_CPU - Port CPU Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.9.8 PTHG - Port GMAC Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.9.9 QOSC00, QOSC01 - Classes Byte Limit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.9.10 QOSC02, QOSC15 - Classes Byte Limit port 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.9.11 QOSC16 - QOSC21 - Classes Byte Limit CPU port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.9.12 QOSC22 - QOSC27 - Classes Byte Limit GMAC port . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.9.13 QOSC28 - QOSC31 - Classes WFQ Credit For GMAC . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.9.14 QOSC36 - QOSC39 - Shaper Control Port GMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.10 (Group E Address) System Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.10.1 DTSRL - Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.2 DTSRM - Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.3 TESTOUT0, TESTOUT1 - Testmux Output [7:0], [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.4 MASK0-MASK4 - Timeout Reset Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.5 BOOTSTRAP0 - BOOTSTRAP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.6 PRTFSMST0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.10.7 PRTQOSST0-PRTQOSST7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.10.8 PRTQOSST8A, PRTQOSST8B (CPU port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.10.9 PRTQOSST9A, PRTQOSST9B (GMAC port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.10.10 CLASSQOSST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.10.11 PRTINTCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.10.12 QMCTRL0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.10.13 QCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.10.14 BMBISTR0, BMBISTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.10.15 BMControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.10.16 BUFF_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.10.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.10.19 FCB_NUM0, FCB_NUM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.10.20 BM_RLSFF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.10.21 BM_RSLFF_INFO[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.3.11 (Group F Address) CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.3.11.1 GCR - Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12.3.11.2 DCR - Device Status and Signature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.3.11.3 DCR1 - Device Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.3.11.4 DPST - Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.3.11.5 DTST - Data read back register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.11.6 DA - Dead or Alive Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Table of Contents
13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.4.2 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.4.3 EEPROM Inter-Integrated Circuit (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4.4 Reduced Media Independent Interface (RMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.4.5 Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.4.6 Reverse Media Independent Interface (RvMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.4.7 General Purpose Serial Interface (GPSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.4.8 Reverse General Purpose Serial Interface (RvGPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.4.9 Gigabit Media Independent Interface (GMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.4.10 MII Management Data Interface (MDIO/MDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.4.11 JTAG (IEEE 1149.1-2001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12
Zarlink Semiconductor Inc.
ZL50407 1.0
1.1
Data Sheet
BGA and Ball Signal Descriptions
BGA Views (Top-View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
SCLK
DATAI N SDA
DATAO UT SCL
STRO BE RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GREF_ CLK TCK
M9_TX CLK TMS
M9_M TXCLK M9_TX ER M9_C RS M9_RX DV M9_TX D6 M9_TX D4 M9_TX D2 M9_TX D0 M7_TX D1 M7_TX EN M7_RX D1 M5_C OL M6_TX CK M6_RX CK M6_TX EN M6_C RS 15
M9_TX EN M9_RX CK M9_C OL M9_RX ER M9_TX D7 M9_TX D5 M9_TX D3 M9_TX D1 M7_TX D0 M7_C RS M7_RX D0 M4_C OL M6_TX D3 M6_TX D2 M6_TX D1 M6_TX D0 16
A
B
P_INT
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
B
C
RESET OUT# RESIN # M2_C OL M_MD C M0_RX D0 M0_C RS M0_TX D0 M1_RX D0 M1_C RS M1_TX D0 M2_RX D3 M2_RX D2 M2_RX D1 M2_RX D0 1
TSTO UT1 TSTO UT0 M0_C OL M_MDI O M0_RX D1 M0_TX EN M0_TX D1 M1_RX D1 M1_TX EN M1_TX D1 M2_TX CK M2_RX CK M2_TX EN M2_C RS 2
TSTO UT3 TSTO UT2 M1_C OL M0_RX D2 M0_RX CK M0_TX D2 M0_TX CK M1_RX D2 M1_TX D2 M1_TX CK M2_TX D3 M2_TX D2 M2_TX D1 M2_TX D0 3
TSTO UT5 TSTO UT4 3.3V
TSTO UT6 3.3V
TSTO UT7 IC_GN D
TSTO UT9 TSTO UT8
TSTO UT11 TSTO UT10
TSTO UT12 1.8V
TSTO UT14 TSTO UT13
TSTO UT15 TDO
TRST#
TDI
M9_RX D7 M9_RX D6 M9_RX D4 M9_RX D3 M9_RX D1 M7_C OL M7_TX CK M7_RX D2 M7_RX CK M6_C OL M6_RX D3 M6_RX D2 M6_RX D1 M6_RX D0 14
C
D
3.3V
M9_RX D5 3.3V
D
E
E
F
M0_RX D3 M0_TX D3 1.8V GND GND GND GND
M9_RX D2 M9_RX D0 1.8V
F
G
G
H
GND
GND
GND
GND
H
J
M1_RX D3 M1_RX CK M1_TX D3 3.3V
GND
GND
GND
GND
M7_TX D3 M7_TX D2 M7_RX D3 3.3V
J
K
GND
GND
GND
GND
K
L
L
M
M
N
M3_RX D3 M3_RX D2 M3_RX D1 M3_RX D0 4
3.3V
M3_TX D3 M3_TX D2 M3_TX D1 M3_TX D0 6
1.8V
M4_RX D3 M4_RX D2 M4_RX D1 M4_RX D0 8
M4_TX CK M4_RX CK M4_TX EN M4_C RS 9
M4_TX D3 M4_TX D2 M4_TX D1 M4_TX D0 10
M5_RX D3 M5_RX D2 M5_RX D1 M5_RX D0 11
M5_TX CK M5_RX CK M5_TX EN M5_C RS 12
M5_TX D3 M5_TX D2 M5_TX D1 M5_TX D0 13
N
P
M3_RX CK M3_TX EN M3_C RS 5
M3_C OL M_CLK
P
R
R
T
M3_TX CK 7
T
1.2
Power and Ground Distribution
G7-10, H7-10, J7-10, K7-10 D5, D12, E4, E13, M4, M13, N5 D9, H4, H13, N7 GND
VSS VCC VDD
Ground I/O Power Core Power
3.3V 1.8V
13
Zarlink Semiconductor Inc.
ZL50407
1.3 Ball Signal Descriptions
Data Sheet
All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive.
Notes #= Input = Input-ST = Output = I/O-TS = pull-up = Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Input & Output signal with Tri-State driver Weak internal pull-up (nominal 100K) (refer to Section 1.4 on page 19 as some internal pull-ups are not enabled in certain configurations) pull-down = Weak internal pull-down (nominal 100K) (refer to Section 1.4 on page 19 as some internal pull-downs are not enabled in certain configurations)
Ball Signal Description Table
Ball No(s)
Symbol
I/O
Description
I2C Interface - Unmanaged Mode Only (TSTOUT[3] bootstrap must be '1') B3 B2 SCL SDA Output w/ pull up I/O-TS w/ pull up I2C - Serial Clock Line Unmanaged Mode Only I2C - Serial Data Line Unmanaged Mode Only
Serial CPU Bus Interface A4 A3 A2 B1 STROBE DATAOUT DATAIN P_INT Input w/ pull up Output Input w/ pull up Output SSI - Clock Signal SSI - Data Out SSI - Data In CPU Interrupt Active high, but can be changed via register DEVICE, bit [1]. Fast Ethernet Access Ports [7:0] MII
L13, K14, L15, L16, N14, P14, R14, T14, N11, P11, R11, T11, N8, P8, R8, T8, N4, P4, R4, T4, N1, P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1
M[7:0]_RXD[3:0]
Input with pull-up
Ports [7:0] - Receive Data Bit [3:0]
14
Zarlink Semiconductor Inc.
ZL50407
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) K16, T15, T12, T9, T5, T2, L1, H1 K15, R15, R12, R9, R5, R2, L2, H2 J13, K13, J15, J16, N16, P16, R16, T16, N13, P13, R13, T13, N10, P10, R10, T10, N6, P6, R6, T6, N3, P3, R3, T3, L4, L3, M2, M1, G4, H3, J2, J1 H14, M14, M15, M16, P7, E1, E3, E2 J14, N15, N12, N9, T7, N2, M3, J3 L14, P15, P12, P9, P5, P2, K4, G3
Symbol M[7:0]_CRS_DV M[7:0]_TXEN
I/O Input with pull-up Output, slew
Description Ports [7:0] - Carrier Sense and Receive Data Valid Ports [7:0] - Transmit Enable This pin also serves as a bootstrap pin.
M[7:0]_TXD[3:0]
Output, slew
Ports [7:0] - Transmit Data Bit [3:0]
M[7:0]_COL M[7:0]_TXCLK
Input with pull-down Input or Output with pull-up Input or Output with pull-up
Ports[7:0] - Collision Ports[7:0] - Transmit Clock This pin in an output if ECR4Pn[1:0]='11'
M[7:0]_RXCLK
Ports[7:0] - Receive Clock This pin in an output if ECR4Pn[1:0]='11'
Gigabit Ethernet Uplink Port GMII E16, E15, F16, F15, G16, G15, H16, H15 D15 D16 C15 C16 B16 M9_TXD[7:0] M9_RXDV M9_RXER M9_CRS M9_COL M9_RXCLK Output Input with pull-up Input with pull-up Input with pull-down Input with pull-down Input or Output with pull-up Transmit Data Bit [7:0] Receive Data Valid Receive Error Carrier Sense Collision Detected Receive Clock In MII mode, this pin in an output if ECR4P9[1:0]='11' C14, D14, D13, E14, F14, F13, G14, G13 A16 M9_RXD[7:0] M9_TXEN Input with pull-up Output with pull-up Receive Data Bit [7:0] Transmit Data Enable This pin also serves as a bootstrap pin.
15
Zarlink Semiconductor Inc.
ZL50407
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) B15
Symbol M9_TXER
I/O Output with pull-up Input with pull-up Output Transmit Error
Description
This pin also serves as a bootstrap pin. A15 A14 Test Interface C11, C10, D10, C9, C8, D8, C7, D7, C6, C5, C4, D4, C3, D3, C2, D2 TSTOUT[15:0] Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Test Facility C13 C12 TDI TRST# Input with pull-up Input with pull-up JTAG - Test Data In JTAG - Test Reset In normal operation, this pin should be pulled low. Recommend weak external pull-down resistor (470 to 1 k). B13 B14 D11 TCK TMS TDO Input with pull-up Input with pull-up Output JTAG - Test Clock JTAG - Test Mode State JTAG - Test Data Out M9_MTXCLK M9_TXCLK Transmit Clock Gigabit Transmit Clock
System Clock, Power, and Ground Pins A1 SCLK Input System Clock. Based on system requirement, SCLK needs to operate at difference frequency. SCLK requires 40/60% duty cycle clock. +1.8 Volt DC Supply +3.3 Volt DC Supply Ground
D9, H4, H13, N7, D5, D12, E4, E13, M4, M13, N5, G7-10, H7-10, J7-10, K7-10 Misc. D1
VDD VCC VSS
Power Power Power Ground
RESIN#
Input
Reset Input
16
Zarlink Semiconductor Inc.
ZL50407
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) C1 F1 F2 R7 A13 A12, B12, A11, B11, A10, B10, A9, B9, A8, B8, A7, B7, A6, B6, A5, B5, B4 D6 Bootstrap Pins1
Symbol RESETOUT# M_MDC M_MDIO M_CLK GREF_CLK RSVD Output Output
I/O Reset PHY
Description
MII Management Data Clock MII Management Data I/O RMAC Reference Clock GMAC Reference Clock Reserved. Leave unconnected.
I/O-TS with pull-up Input Input with pull-up N/A
IC_GND
IC_GND
Internal Connect. Tie to ground (VSS) via 1 K resistor.
External pull-up/down resistors are required on all bootstrap pins for proper operation. See "Bootstrap Options" on page 21 for more information. D2 TSTOUT[0] Input (Reset Only) Enable Debounce on SSI interface Pullup - Enabled Pulldown - Disabled When enabled, DATAOUT is an open-drain output; when disabled, DATAOUT is a totem-pole output. See "Synchronous Serial Interface (SSI)" on page 121 for more details on debounce timing. D3, C2 TSTOUT[2:1] Input (Reset Only) Must be externally pulled-up C3 TSTOUT[3] Input (Reset Only) Management interface operation mode: Pulldown - Lightly Managed Serial. CPU can transmit/receive frames with the serial interface. Pullup - Unmanaged Serial. No CPU packet can be transmit or received with the serial interface. EEPROM can be used to configure the device at bootup. A one (1) indicates pullup. A zero (0) indicates pulldown. Reserved. Must be pulled up.
17
Zarlink Semiconductor Inc.
ZL50407
Ball Signal Description Table (continued)
Data Sheet
Ball No(s) C5, C4, D4
Symbol TSTOUT[6:4]
I/O Input (Reset Only)
Description Device ID. Default address of the device for serial interface. Up to 8 device can be sharing the serial management bus with different device ID. A one (1) indicates pullup. A zero (0) indicates pulldown. TSTOUT[4] is the Least Significant Bit (LSB).
C6
TSTOUT[7]
Input (Reset Only)
EEPROM not installed. Pullup: Not installed Pulldown: Installed Manufacturing Option. Must be pulled up.
D7
TSTOUT[8]
Input (Reset Only) Must be externally pulled-up
C7
TSTOUT[9]
Input (Reset Only)
Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose). Pulldown: Disable Manufacturing Option. Must be pulled down.
D8
TSTOUT[10]
Input (Reset Only) Must be externally pulled-down
C8
TSTOUT[11]
Input (Reset Only)
Power Saving Pullup: Enable MAC power saving mode Pulldown: Disable MAC power saving mode Timeout Reset Enable Pullup: Enable Pulldown: Disable Manufacturing Options. Must be pulled-up.
C9
TSTOUT[12]
Input (Reset Only)
C11, C10, D10
TSTOUT[15:13]
Input (Reset Only) Must be externally pulled-up
K15, R15, R12, R9, R5, R2, L2, H2
M[7:0]_TXEN
Input (Reset Only)
User Defined Bootstrap: Usually used in conjuction with Module Detect to determine what interface to use for the inserted module. Can be read from BOOTSTRAP2 register User Defined Bootstrap: Usually used in conjuction with Module Detect to determine what interface to use for the inserted module. Can be read from BOOTSTRAP3 register
A16, B15
M9_TXEN, M9_TXER
Input with pull-up (Reset Only)
1. Note: 1=pull-up; 0=pull-down
18
Zarlink Semiconductor Inc.
ZL50407
1.4 Signal Mapping and Internal pull-up/Down Configuration
Data Sheet
The ZL50407 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the "Ball Signal Description Table" on page 14. It also specifies whether the internal pull-up/down resistor is present for each pin in the specific operating mode.
Notes: I - Input O - Output U - Pullup D - Pulldown
Fast Ethernet Access Ports Pin Symbol M[7:0]_RXD0 M[7:0]_RXD1 M[7:0]_RXD2 M[7:0]_RXD3 M[7:0]_TXEN M[7:0]_CRS_DV M[7:0]_TXD0 M[7:0]_TXD1 M[7:0]_TXD2 M[7:0]_TXD3 M[7:0]_COL M[7:0]_TXCLK M[7:0]_RXCLK
No Module
(Bootstrap TSTOUT9='1')
RMII Mode
(ECR4Pn[4:3]='11')
MII Mode
(ECR4Pn[4:3]='01')
GPSI Mode
(ECR4Pn[4:3]='00')
(U) (U) (U) (U) (O) (U) (O) (O) (O) (O) (D) (U) (U)
M[7:0]_RXD0 (I) M[7:0]_RXD1 (I) NC (U) NC (U) M[7:0]_TXEN (O) M[7:0]_CRS_DV (I) M[7:0]_TXD0 (O) M[7:0]_TXD1 (O) NC (O) NC (O) NC (D) NC (U) NC (U)
M[7:0]_RXD0 (I) M[7:0]_RXD1 (I) M[7:0]_RXD2 (I) M[7:0]_RXD3 (I) M[7:0]_TXEN (O) M[7:0]_DV (I) M[7:0]_TXD0 (O) M[7:0]_TXD1 (O) M[7:0]_TXD2 (O) M[7:0]_TXD3 (O) M[7:0]_COL (I) M[7:0]_TXCLK (IO) M[7:0]_RXCLK (IO)
M[7:0]_RXD (I) NC (U) NC (U) NC (U) M[7:0]_TXEN (O) M[7:0]_CRS (I) M[7:0]_TXD (O) NC (O) NC (O) NC (O) M[7:0]_COL (I) M[7:0]_TXCLK (IO) M[7:0]_RXCLK (IO)
Table 1 - Signal Mapping In Different Operation Mode
19
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
The ZL50407 Gigabit Ethernet uplink port (port 9) supports 2 interface options: GMII & MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in "Ball Signal Description Table" on page 14.
Gigabit Ethernet Uplink Port Pin Symbol M9_RXD0 M9_RXD1 M9_RXD2 M9_RXD3 M9_RXD4 M9_RXD5 M9_RXD6 M9_RXD7 M9_RXDV M9_RXER M9_CRS M9_COL M9_RXCLK M9_TXD0 M9_TXD1 M9_TXD2 M9_TXD3 M9_TXD4 M9_TXD5 M9_TXD6 M9_TXD7 M9_TXEN M9_TXER M9_TXCLK GREF_CLK M9_MTXCLK
No Module
(Bootstrap TSTOUT9='1')
GMII Mode
(ECR4P9[4:3]='11')
MII Mode
(ECR4P9[4:3]='00')
(U) (U) (U) (U) (U) (U) (U) (U) (U) (U) (D) (D) (U) (O) (O) (O) (O) (O) (O) (O) (O) (U) (U) (O) (U) (U)
M9_RXD0 (I) M9_RXD1 (I) M9_RXD2 (I) M9_RXD3 (I) M9_RXD4 (I) M9_RXD5 (I) M9_RXD6 (I) M9_RXD7 (I) M9_RXDV (I) M9_RXER (I) M9_CRS (I) M9_COL (I) M9_RXCLK (I) M9_TXD0 (O) M9_TXD1 (O) M9_TXD2 (O) M9_TXD3 (O) M9_TXD4 (O) M9_TXD5 (O) M9_TXD6 (O) M9_TXD7 (O) M9_TXEN (O) M9_TXER (O) M9_TXCLK (O) GREF_CLK (I) M9_MTXCLK (I)
M9_RXD0 (I) M9_RXD1 (I) M9_RXD2 (I) M9_RXD3 (I) NC (U) NC (U) NC (U) NC (U) M9_RXDV (I) M9_RXER (U) M9_CRS (I) M9_COL (I) M9_RXCLK (IO) M9_TXD0 (O) M9_TXD1 (O) M9_TXD2 (O) M9_TXD3 (O) NC (O) NC (O) NC (O) NC (O) M9_TXEN (O) M9_TXER (O) NC (O) REF_CLK (I) M9_MTXCLK (I)
Table 2 - Signal Mapping In Different Operation Mode
20
Zarlink Semiconductor Inc.
ZL50407
1.5 Bootstrap Options
Data Sheet
TSTOUT[15:0], M[7:0]_TXEN, M9_TXEN and M9_TXER pins serve as bootstrap pins during device power-up or reset. Please refer to "Typical Reset & Bootstrap Timing Diagram" on page 120 for more information on when the bootstrap pins are sampled. The bootstrap pins require external pull-up/down resistors for proper operation. Recommend 10 K for pull-ups and 1 K for pull-downs. The table below summarizes the bootstrap options.
Feature CPU Interface
Description The ZL50407 allows the selection of 2 different management interfaces: serial only and unmanaged serial with I2C EEPROM. TSTOUT[3] is used to select the interface options mentioned above. If the serial interface is selected, addition bootstrap options are required: * TSTOUT[0] enables or disables the DEBOUNCE feature (refer to "Synchronous Serial Interface" on page 31) * TSTOUT[6:4] selects the device ID Also, in unmanaged mode, an optional I2C EEPROM can be used to configure the device at power-up or reset. TSTOUT[7] selects the EEPROM option.
Ethernet Interface
The ZL50407 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) and M9-TXEN & M9_TXER (port 9) are used to specify the module type to support multiple ethernet interfaces during module hotswap. Another feature is the MAC power savings mode. When enabled via TSTOUT[11], each port's MAC will detect inactivity on the port and go into a power savings state. When activity is detected once again on the port, the MAC will come out of this state.
Misc. Features
One other feature selected via bootstrap is Timeout Reset Enable (TSTOUT[12]). This enables a monitoring block with the device which will detect if any hardware state machine is in a non-idle state for more than 5 seconds. Refer to section 2.7 for more details on this feature. Table 3 - Bootstrap Features
1.5.1
Recommended Default Bootstrap Settings
The following are the recommended default settings for the bootstrap options: * Unmanaged/Lightly Managed * Reserved/Manufacturing bootstraps - TSTOUT[15:13,8,2,1] must be pulled-up - TSTOUT[10] must be pulled-down * CPU Interface: - Strobe debounce bootstrap, TSTOUT[0], should be normally pulled-up, unless you wish to disable the debounce logic - CPU Interface bootstrap, TSTOUT[3], should be pulled-up to indicate unmanaged SSI CPU interface. To enable lightly managed mode, pulled-down - SSI Device ID bootstrap, TSTOUT[6:4], should be pulled-down to indicate device ID 0x0 for the SSI interface. Can be changed to whatever device ID required if more than one device on the SSI bus.
21
Zarlink Semiconductor Inc.
ZL50407
-
Data Sheet
EEPROM bootstrap, TSTOUT[7], should be pulled-up to disable until the system is debugged. You can pull-down this bootstrap if using the optional EEPROM in unmanaged mode (NOTE: this bootstrap is not valid in any other CPU mode) * Module Detect bootstrap, TSTOUT[9], should be pulled-down - In lightly managed mode, you can enable the optional Module Detect feature - If enabled, need to use Mn_TXEN to indicate module type * Power Saving bootstrap, TSTOUT[11], should be normally pulled-up * Timeout Reset bootstrap, TSTOUT[12], should be pull-down - Once system is debugged, you can enable the optional feature with pull-up (Refer to section 2.7 for more details on this feature)
1.6
Default Switch Configuration and Initialization Sequence
The ZL50407 will come out of reset in a default configuration, which will allow for basic L2 switching and automatic MAC address learning. In unmanaged mode, the default configuration will take effect immediately after reset. The default settings can be changed using the optional EEPROM. * System Defaults * Port-based VLAN * MAC address 00-00-00-00-00-00 not learned * Drop MAC addresses 01-80-C2-00-00-01~F * Trunking and mirroring disabled * MAC address agetime is 300 seconds * VLAN 802.1p prioritization - All priority bits mapped to priority 0 (lowest) * 96 queued unicast/multicast frames will trigger flow control * All WRED drop percentages equal to 0% * Unicast/multicast/broadcast flood control disabled * No shared or per-class buffer pools Per-port Defaults * Disable per-port fixed priority and drop precedence * Disable asynchronous flow control * Spanning Tree per-port state equal to forwarding * Don't filter tagged/untagged VLAN frames * Automatic learning enabled * Per-port security disabled * Support frame size 64 <= n <= 1522 * Pad transmit frames < 64B * Standard preamble * Strict Priority scheduling * FE Ports - RMII mode - Auto-negotiate 10/100 M, Full Duplex, Flow Control - Rate control disabled - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers * Uplink Port - GMII mode - Auto-negotiate 10/100/1000 M, Full Duplex, Flow Control - per-source port buffer pool of 384 buffers, with flow control threshold of 192 buffers
*
22
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
In lightly managed mode, the default configuration can be used as well, however, the device needs to be told when to start switching. This is done via the "Init Complete" bit, set in GCR[4]. The default settings can be overridden using the CPU interface, but should be done before setting of GCR[4]. One thing to note is after reset, the device will start to initialize the control tables. Therefore, a short delay (100 us~1 ms) is necessary before changing the register settings and/or control tables, and before setting GCR[4]. * System Defaults * CPU MAC address is 00-00-00-00-00-00 * Forward MAC addresses 01-80-C2-00-00-00~F to CPU port - Except 01-80-C2-00-00-01~F, which are dropped * All interrupts enabled * MAC address learn report to CPU disabled * Statistics counters disabled * DiffServ EF code support disabled * No VLAN ID hashing Per-port Defaults * FE Ports - Link heart beat disabled * CPU Port - 100 M, Full Duplex, Flow Control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers
*
1.7
Power Sequencing
The ZL50407 has two separate power supplies: VDD (1.8 V) and VCC (3.3 V). The recommended power-up sequence is for VCC to be applied first, followed by the VDD supply. VCC should lead VDD supply by at least 0.2 V, but by no more than 2 V. Both supplies may be powered-down simultaneously.
I/O supply (VCC = 3.3V)
VDC
>0.2 VDC
Core supply (VDD = 1.8V)
t
RESIN
t
> 10 s
SCLK
t
10 ns
Figure 2 - Power-up Sequence See "Typical Reset & Bootstrap Timing Diagram" on page 120 for more details on reset and bootstrap sampling.
23
Zarlink Semiconductor Inc.
ZL50407 2.0 Block Functionality
Data Sheet
8 Fast Ethernet Ports
Fast Ethernet MAC Interface
(RMII/MII/GPSI)
Frame Engine & Queuing
Per -Class Traffic Shaping, SP/WFQ Scheduling, Congestion WRED
Uplink MAC Interface
Gigabit Ethernet Port
192 KB
Frame Buffer Memory
Network Management Database & RMON Counters
64 KB
Switch Control Databases
L2 Search Engine
Single - Field Classifier, 4K MAC Addresses
Management Module
I 2 C & Serial Interface JTAG
MDIO Interface
Figure 3 - Functional Block Diagram
2.1
Internal Memory
Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table database (MCT), and the Network Management (NM) Database statistics counters and MIB. The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the egress port. A memory arbiter is used to arbitrary the memory access requests from various sources. A Built In Self Test (BIST) is used to detect any error in the memory array when the device is powered up. The BIST can also be requested by the writing to the GCR register.
2.2 2.2.1
MAC Modules RMII MAC Module (RMAC)
The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50407 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. These eight ports are denoted as ports 0 to 7. The PHY addresses for the PHY devices connected to the 8 RMAC ports has to be from 08h (port 0) to 0Fh (port 7).
24
Zarlink Semiconductor Inc.
ZL50407
2.2.1.1 GPSI (7WS) Interface
Data Sheet
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX data and respectively. The link and duplex of the port can be controlled by programming the ECR1Pn register. Only port-based VLAN is supported with GPSI interface.
2.2.2
CPU MAC Module (CMAC)
The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external CPU device. It support a register access mechanism via the serial interface. This port is denoted as port 8.
2.2.3
GMII MAC Module (GMAC)
The GMII Media Access Control (GMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1G. The GMAC of the ZL50407 device meets the IEEE 802.3Z specification. It is able to operate in 10 M/100 M either Half or Full Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. This port is denoted as port 9. The PHY address for the PHY device connected to the GMAC port has to be 10h.
2.2.4
PHY Addresses
The table below provides an overview of the PHY addresses required for each port in order for the MDIO auto-negotiation to work between the ZL50407 MAC and the PHY device. If a different PHY address is used, then the port must be manually brought up and the PHY will need to be polled for link status via the MIIC/D registers. MAC Port RMAC Port 0 RMAC Port 1 ... RMAC Port 7 CMAC Port 8 GMAC Port 9 PHY Address 0x08 0x09 ... 0x0F NA 0x10 Table 4 - PHY Addresses
2.3
Management Module
The CPU can send a control frame to access or configure the internal network management database. The Management Module decodes the control frame and executes the functions requested by the CPU. This module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device.
2.4
Frame Engine
The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine, to resolve the destination port. The arriving frame is moved to the internal memory. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent.
25
Zarlink Semiconductor Inc.
ZL50407
2.5 Search Engine
Data Sheet
The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2) by searching the database. It also performs unicast MAC learning, trunking functions, and priority assignment.
2.6
Heartbeat Packet Generation and Response
The ZL50407 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period, If a reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link. The failover detection module will then interrupt the CPU. The LHB packet response module can also reply to LHB messages initiated by other ZL50407 devices in the system, or by non-ZL50407 devices which use a conventional and recognizable LHB message format.
2.7
Timeout Reset Monitor
The ZL50407 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin (TSTOUT12). It also requires some register configuration via the CPU interface. See Programming Timeout Reset application note, ZLAN-41, for more information.
2.8
JTAG
An IEEE1149.1 compliant test interface is provided for boundary scan. The JTAG interface, collectively known as a Test Access Port, or TAP, uses the following signals to support the operation of boundary scan: * * * * * TCK - the TCK or `test clock' synchronizes the internal state machine operations TMS - the TMS or `test mode state' is sampled at the rising edge of TCK to determine the next state TDI - the TDI or `test data in' represents the data shifted into the device's test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state TDO - the TDO or `test data out' represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state TRST - the TRST or `test reset' is an optional pin which, when available, can reset the TAP controller's state machine
2.8.1
Registers
There are two types of registers associated with boundary scan. Each compliant device has one instruction register and two or more data registers. * Instruction Register - the instruction register holds the current instruction. Its content is used by the TAP controller to decide what to do with signals that are received. Most commonly, the content of the instruction register will define to which of the data registers signals should be passed. Data Registers - there are three primary data registers, the Boundary Scan Register (BSR), the BYPASS register and the IDCODES register. Other data registers may be present, but they are not required as part of the JTAG standard. * BSR - this is the main testing data register. It is used to move data to and from the `pins' on a device. * BYPASS - this is a single-bit register that passes information from TDI to TDO. It allows other devices in a circuit to be tested with minimal overhead. * IDCODES - this register contains the ID code and revision number for the device. This information allows the device to be linked to its Boundary Scan Description Language (BSDL) file. The file contains details of the Boundary Scan configuration for the device.
*
26
Zarlink Semiconductor Inc.
ZL50407
2.8.2 Test Access Port (TAP) Controller
Data Sheet
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the behaviour of the JTAG system. For more detail on each state, refer to the IEEE 1149.1 Standard JTAG document.
2.8.3
Boundary Scan Instructions
The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be considered compliant. These instructions are: * BYPASS - the BYPASS instruction causes the TDI and TDO lines to be connected via a single-bit pass-through register (the BYPASS register). This instruction allows the testing of other devices in the JTAG chain without any unnecessary overhead. EXTEST - the EXTEST instruction causes the TDI and TDO to be connected to the Boundary Scan Register (BSR). The device's pin states are sampled with the `capture dr' JTAG state and new values are shifted into the BSR with the `shift dr' state; these values are then applied to the pins of the device using the `update dr' state. SAMPLE/PRELOAD - the SAMPLE/PRELOAD instruction causes the TDI and TDO to be connected to the BSR. However, the device is left in its normal functional mode. During this instruction, the BSR can be accessed by a data scan operation to take a sample of the functional data entering and leaving the device. The instruction is also used to preload test data into the BSR prior to loading an EXTEST instruction.
*
*
Other available instructions for the ZL50407 include: * * IDCODE - the IDCODE instruction causes the TDI and TDO to be connected to the IDCODE register. HIGHZ - the HIGHZ instruction causes all of the logic outputs to be placed in an inactive drive state (e.g., high impedance).
3.0
Management and Configuration
One extra port is dedicated to the CPU via the CPU interface module. Two modes this port can operate: lightly managed or unmanaged mode. The different between these modes is tx/rx Ethernet frame, tx/rx control frame and receiving interrupt due to the lack of constant attention or processing power from the CPU. Supported CPU interface modes are Operation Mode Lightly Managed Serial Unmanaged Serial ISA Interface NA NA Yes Yes Serial No No MII No Yes IC
Table 5 - Supported CPU interface modes 1. Lightly Managed Serial. Configuration registers access, Control frame and CPU transmit/receive packets are sent through a synchronous serial interface (SSI) bus. 2. Unmanaged Serial. The device can be configured by EEPROM using an IC interface at bootup, or via a synchronous serial interface (SSI) otherwise. All configuration registers and internal control blocks are accessible by the interface. However, the CPU cannot receive or transmit frames nor will it receive any interrupt information. The CPU interface provides for easy and effective management of the switching system.
27
Zarlink Semiconductor Inc.
ZL50407
Figure 4 on page 28 provides an overview of the SSI interface.
Data Sheet
Processor
Serial Out Serial In Strobe Interrupt
Synchronous Serial Interface
3-bit Address Bus 16-bit Data Bus INT CSW R
Address
I/O DataMUX
Index Reg 0 (Addr = 0)
Conf igData Reg (Addr = 2)
CPU FrameReg (Addr = 3)
Command/ Status Reg (Addr = 4)
Interrupt Reg (Addr = 5)
ControlCommand 1 Reg (Addr = 6)
Control Command2 Reg (Addr = 7)
8/16-bit Data Bus 8-bit Data Bus 16-bit Address
Internal Registers Inderect Access CPU f rame Transmit CPU f rame Receiv e FIFO FIFO Control Control Command1 Command1Transmit Receiv e FIFO FIFO Control Command2 Transmit FIFO
8/16-bit Data Bus
Interrupt
Figure 4 - Overview of the SSI Interface
3.1 3.1.1
Register Configuration, Frame Transmission and Frame Reception Register Configuration
The ZL50407 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: * In serial mode, the address, command and data are shifted in serially. To access the configuration registers, an "index" register (addresses 000b) needs to be written with the configuration register address. The desired data can be written into or read from the "data" register (address 010b). * For example, if "XX" is required to be written to register "YY", a write of "YY" is required to write to address "000b" (Index register). Then, a write of "XX" is required to write to address "010b" (Data Register). This completes the register write and register "YY" will contain the value of "XX".
28
Zarlink Semiconductor Inc.
ZL50407
*
Data Sheet
To indirectly configure the register addressed by the index register, a "data" register (address 010b) must be written with the desired 8-bit data. * The ZL50407 supports special register-write in serial mode. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of configuration register address, CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address specified in index register and upper 8 bit of data is for the address + 1.
15 INC R/W 14 SP W 13 12 11 12 Bit Register Address 0
Reserved
* *
Similarly, to read the value in the register addressed by the index register, the "data" register can now simply be read. The ZL50407 supports an incremental read/write. If CPU requires to read or write to the configuration registers incrementally, CPU only has to write to index register once with the MSB of configuration register address set and then CPU can continuously reading or writing to "data" register (010b).
In summary, access to the many internal registers is carried out simply by directly accessing only two registers - one register to indicate the index of the desired parameter, and one register to read or write a value. Of course, because there is only one bus master, there can never be any conflict between reading and writing the configuration registers.
3.1.2
Rx/Tx of Standard Ethernet Frames
In serial only mode, the Ethernet frame is transmitted and received through the CPU interface. There is no ability to send/receive Ethernet frames in unmanaged mode. To transmit a frame from the CPU in serial only mode: * The CPU writes to the "data frame" register (address 011) with the frame size, destination port number, and frame status. After writing all the transmitting status bytes, it then writes the data it wants to transmit (minimum 64 bytes). The ZL50407 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact that the frame originated from the CPU.
*
To receive a frame into the CPU in serial only mode: * * * The CPU receives an interrupt when an Ethernet frame is available to be received. Frame information arrives first in the data frame register. This includes source port number, frame size, and VLAN tag. The actual data follows the frame information. The CPU uses the frame size information to read the frame out.
In summary, in serial only mode, receiving and transmitting frames to and from the CPU is a simple process that uses one direct access register only.The details of sending an Ethernet Frame via the CPU interface is described in the Processor Interface Application Note, ZLAN-26. Although there is the ability to Tx/Rx Ethernet Frames via the serial interface in lightly managed mode, the ZL50407 is not meant to be used in a fully managed system. The speed of the serial interface limits management capability. For example, if the system is trying to implement port security, it would require a faster interface between the CPU and the ZL50407, such as the 8/16-bit interface or the serial + MII interface found on the managed device.
3.1.3
Control Frames
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle special "Control frames," generated by the ZL50407 and sent to the CPU. These proprietary frames are related to such tasks as statistics collection, MAC address learning, and aging, etc. All Control frames are up to 40 bytes long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that the register accessed is the "Control frame data" register (address 111).
29
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Specifically, there are the following types of control frames generated by the CPU and sent to the ZL50407: * * * * * Memory read request Memory write request Learn Unicast MAC address Delete Unicast MAC address Search Unicast MAC address
Note: Memory read and write requests by the CPU may include all internal memories which include statistic counters, MAC address control link table and the 2 Mbit (256 KB) memory block. In addition, the following types of Control frames are generated by the ZL50407 and sent to the CPU: * * * * * Interrupt CPU when statistics counter rolls over Response to memory read request from CPU Learn Unicast MAC address Delete Unicast MAC address Response to search Unicast MAC address request from CPU
The format of the Control Frame is described in the Processor Interface application note, ZLAN-26. Although there is the ability to Tx/Rx Control Frames via the serial interface in lightly managed mode, the ZL50407 is not meant to be used in a fully managed system. The speed of the serial interface limits management capability. For example, if the system is trying to manage the MAC learning/deletion, it would require a faster interface between the CPU and the ZL50407, such as the 8/16-bit interface found on the managed device.
3.2
I2C Interface
The IC interface serves the function of configuring the ZL50407 at boot time. The master is the ZL50407, and the slave is the EEPROM memory. The IC interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 5 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to "ZL50407 Register Description" on page 56 for IC address for each register.
START SLAVE ADDRESS R/W ACK DATA 1 (8bits) ACK DATA 2 ACK DATA M ACK STOP
Figure 5 - Data Transfer Format for IC Interface
3.2.1
Start Condition
Generated by the master (in our case, the ZL50407). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the IC bus is free, both lines are High.
3.2.2
Address
The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address.
30
Zarlink Semiconductor Inc.
ZL50407
3.2.3 Data Direction
Data Sheet
The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R.
3.2.4
Acknowledgment
Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull-down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition.
3.2.5
Data
After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first.
3.2.6
Stop Condition
Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line.
3.3
Synchronous Serial Interface
The synchronous serial interface (SSI) serves the function of configuring the ZL50407 not at boot time but via a PC. The PC serves as master and the ZL50407 serves as slave. The protocol for the synchronous serial interface is nearly identical to the IC protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time. 3 ID bits are used to allow up to eight ZL50407 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. To reduce the number of signals required, the register address, command and data are shifted in serially through the DATAIN pin. STROBE- pin is used as the shift clock. DATAOUT pin is used as data return path. Each command consists of four parts. * * * * START pulse Register Address Read or Write command Data to be written or read back
Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50407. Read operation can only be aborted before issuing the read command to the ZL50407. A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low when STROBE- fall. An ABORT command is detected when DATAIN is sampled low when STROBE- rise and DATAIN is sampled high when STROBE- fall.
31
Zarlink Semiconductor Inc.
ZL50407
3.3.1 Write Command
Data Sheet
All registers in ZL50407 can be modified through this synchronous serial interface. Once the data has been sent, two extra STOBE clocks must be generated to indicate the end of the write command. The DATAIN line is ignored for these two pulses.
STROBE 2 Extra clocks after last transfer DATAIN ID0 START ID1 ID ID2 A0 A1 ADDR A2 W CMD D0 D1 D2 D3 ... D12 D13 D14 D15
DATA
Figure 6 - Serial Interface Write Command Functional Timing
3.3.2
Read Command
All registers in ZL50407 can be read through this synchronous serial interface.
STROBE
DATAIN
ID0 START
ID1 ID
ID2
A0
A1 ADDR
A2
R CMD DATA ...
DATAOUT
D0
D1
D2
D12
D13
D14
D15
Figure 7 - Serial Interface Read Command Functional Timing
4.0
4.1
Data Forwarding Protocol
Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (SRAM) interface is a 64-bit bus, connected to internal memory block. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn", the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests. The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-port-per-class TxQ. The switch response will come with 8 classified results. The TxQ manager will map this result into the per-port-per-class queue. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 2
32
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
transmission classes for each of the 8 RMAC ports, and 4 classes for the GMAC and CPU ports - a total of 24 unicast queues. The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line.
4.2
Multicast Data Frame Forwarding
After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 8 RMAC ports. There are 4 multicast queues for the GMAC and CPU ports. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the GMAC and CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the space in the internal memory block. The size and starting address can also be programmed through memory configuration command. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined.
4.3
Frame Forwarding To and From CPU
Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between transmission ports. The only difference is that the physical destination port must be indicated in addition to the destination MAC address. Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only difference is in frame scheduling. Instead of using the patent-pending Zarlink Semiconductor scheduling algorithms, scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue. There are four output queues to the CPU and one receive queue.
33
Zarlink Semiconductor Inc.
ZL50407 5.0
5.1
Data Sheet
Search Engine
Search Engine Overview
The ZL50407 search engine is optimized for high throughput searching, with enhanced features to support: * * * * * * * Up to 4 K of Unicast MAC addresses Up to 8 groups of port trunking Traffic classification into 2 (or 4 for GMAC) transmission priorities, and 2 drop precedence levels Packet filtering based on MAC address, Protocol or Logical Port number Security Individual Flooding, Broadcast, Multicast Storm Control MAC address learning and aging
5.2
Basic Flow
Shortly after a frame enters the ZL50407 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the packet's VLAN ID, and whether the frame is unicast or multicast or broadcast. Requests are sent to the SRAM to locate the associated entries in the MCT table. When all the information has been collected from the SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. The selection of the port within the trunk that will transmit the frame is computed using a hash of the source and/or destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier. The search engine also interacts with the CPU with regard to learning and aging.
5.3 5.3.1
Search, Learning and Aging MAC Search
The search block performs source MAC address and destination MAC address searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. In port based VLAN mode, a bit map is used to determine whether the frame should be forwarded to the outgoing port. The main difference in this mode is that the bit map is not dynamic. Ports cannot enter and exit groups because of real-time learning made by a CPU. The MAC search block is also responsible for updating the source MAC address timestamp used for aging. Moreover, if port trunking is enabled, this block selects the destination port (among those in the trunk group).
34
Zarlink Semiconductor Inc.
ZL50407
5.3.2 Learning
Data Sheet
The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. When CPU reporting is enabled, learning and port change will be performed when the CPU request queue has room, and a "Learn MAC Address" message is sent to the CPU.
5.3.3
Aging
Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table, and a "Delete MAC Address" message is sent to inform the CPU. Supported MAC entry types are: dynamic, static, source filter, destination filter, source and destination filter, and secure MAC addresses. Only dynamic entries can be aged; all others are static. The entry type is stored in the "status" field of the MCT data structure.
5.4
MAC Address Filtering
The ZL50407's implementation of intelligent traffic switching provides filters for source and destination MAC addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. MAC address filtering allows the ZL50407 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem.
5.5
Protocol Filtering
Packet filtering can be performed based on protocol type field in the packets. Up to eight protocols can be programmed to filter or allow packet to pass through the switch.
5.6
Logical Port Filtering
Similar to protocol filtering, if the packet's logical ports match the programmable registers, the packet can be filtered or passed through the switch. Up to eight programmable ports and one ranges can be assigned.
5.7
Quality of Service
Quality of Service (QoS) refers to the ability of a network to provide better service to selected network traffic over various technologies. Primary goals of QoS include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. Traditional Ethernet networks have had no prioritization of traffic. Without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. In a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. The advent of QoS for packet-based systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing Ethernet network. It also alleviates the congestion issues that have previously plagued such "best effort" networking systems. QoS provides Ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed minimum amount of bandwidth.
35
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Extensive core QoS mechanisms are built into the ZL50407 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50407, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. Frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. For example, the overall service given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. The ZL50407 supports the following QoS techniques: * * * In a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority. In a tag-based setup, a 3-bit field in the VLAN tag provides the priority of the packet. This priority can be mapped to different queues in the switch to provide QoS. In a TOS/DS-based set up, TOS stands for "Type of Service" that may include "minimize delay," "maximize throughput," or "maximize reliability." Network nodes may select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. In a logical port-based set up, a logical port provides the application information of the packet. Certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as VoIP.
*
5.8
Priority Classification Rule
Figure 8 shows the ZL50407 priority classification rule.
Fix Port Priority? No
Yes
Use Default port settings
TOS Precedence over VLAN? (QOSC Register bit 5) No
Yes
Use VLAN priority
Yes
VLAN Tag? No
No
IP Frame? Yes
IP Frame? No Use Default port settings
Yes
Use Logical Port? Yes Use logical port
No Use TOS
Figure 8 - Priority Classification Rule
36
Zarlink Semiconductor Inc.
ZL50407
5.9 Port Based VLAN
Data Sheet
An administrator can use the PVMAP Registers to configure the ZL50407 for port-based VLAN (see "Register Definition" on page 56). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50407 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50407 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded.
Destination Port Numbers Bit Map Port Registers Register for Port #0 PVMAP00_0[7:0] to PVMAP00_1[1:0] Register for Port #1 PVMAP01_0[7:0] to PVMAP01_1[1:0] Register for Port #2 PVMAP02_0[7:0] to PVMAP02_1[1:0] ... Register for Port #9 PVMAP09_0[7:0] to PVMAP09_1[1:0] 0 0 0 0 9 0 0 0 ... 2 1 1 0 1 1 0 0 0 0 1 0
Table 6 - Port-Based VLAN Mapping For example, in the above table a 1 denotes that an outgoing port is eligible to receive a packet from an incoming port. A 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. In this example: * * * Data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. Data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2. Data packets received at port #2 are NOT eligible to be sent to ports 0 and 1.
6.0
6.1
Frame Engine
Data Forwarding Summary
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface. A switch request is sent to the Search Engine. The Search Engine processes the switch request. A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast, and its destination port or ports. On receiving the response, the Frame Engine will check all the QoS related information and decide if this frame can be forwarded. A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling Queue (TxSch Q) or Queues. There are 2 TxSch Q for each RMAC port (and 4 per GMAC and CPU ports), one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). (The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older HOL between the two queues goes first.
37
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port.
6.2
Frame Engine Details
This section briefly describes the functions of each of the modules of the ZL50407 frame engine.
6.2.1
FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. The FCB manager is also responsible for enforcing buffer reservations and limits that will be used for QoS control and source port flow control. The default values can be determined by referring to Section 7.6 on page 41. The frame buffer is managed in a 128bytes block unit. During initialization, this block will link all the available blocks in a free buffer list. When each port is ready to receive, this module hands the buffer handle to each requesting port. The FCB manager will also link the released buffer back into the free buffer list. The maximum buffer size can be increased from the standard 1518 bytes (1522 with VLAN tag) to up to 4 K bytes. This is done using BUF_LIMIT, and is enabled on a per port basis via bit [1] in ECR3Pn. See Buffer Allocation application note, ZLAN-47, for more information.
6.2.2
Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch request.
6.2.3
RxDMA
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made.
6.2.4
TxQ Manager
First, the TxQ manager checks the per-class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. The dropping decision includes the head-of-link blocking avoidance if the source port is not flow control enabled. If the decision is not to drop, the TxQ manager links the unicast frame's FCB to the correct per-port-per-class TxQ and updates the FCB information. If multicast, the TxQ manager writes to the multicast queue for that port and class and also update the FCB information including the duplicate count for this multicast frame. The TxQ manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. Second, the TxQ manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. Once a frame has been scheduled, the TxQ manager reads the FCB information and writes to the correct port control module. The detail of the QoS decision guideline is described in chapter 5.
6.2.5
Port Control
The port control module calculates the SRAM read address for the frame currently being transmitted. It also writes start of frame information and an end of frame flag to the MAC TxFIFO. When transmission is done, the port control module requests that the buffer be released.
6.2.6
TxDMA
The TxDMA multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules.
38
Zarlink Semiconductor Inc.
ZL50407 7.0
7.1
Data Sheet
Quality of Service and Flow Control
Model
Quality of service is an all-encompassing term for which different people have different interpretations. In general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. We also assume that the incoming traffic is not policed or shaped. Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist of bandwidth or latency assurances per class. Sometimes it may even reflect an estimate of the traffic mix offered to the switch. As an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch's performance. A class is capable of offering traffic that exceeds the contracted bandwidth. A well-behaved class offers traffic at a rate no greater than the agreed-upon rate. By contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. A misbehaving class is formed from an aggregation of misbehaving microflows. To achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. However, such leniency must not degrade the quality of service (QoS) received by well-behaved classes. Each traffic type may each have their own distinct properties and applications. Classes may receive bandwidth assurances or latency bounds. For example, the highest transmission class may require that all frames receive 50% of the 100 Mbps of bandwidth at that port. Best-effort (P0) traffic forms a class that only receives bandwidth when none of the other classes have any traffic to offer. It is also possible to add a class that has strict priority over all others; if this class has even one frame to transmit, then it goes first. In the ZL50407, each RMAC port will support two total classes, and the GMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section. In addition, each transmission class has two subclasses, high-drop and low-drop. Well-behaved users should rarely lose packets. But poorly behaved users-users who send frames at too high a rate - will encounter frame loss, and the first to be discarded will be high-drop. Of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. For example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas VoIP fits into the category of low-loss, low-latency traffic.
7.2
Two QoS Configurations
There are two basic pieces to QoS scheduling in the GMAC port of ZL50407: strict priority (SP) or weighted fair queuing (WFQ). The only configuration for a RMAC and CPU port is strict priority between the queues.
7.2.1
Strict Priority
When strict priority is part of the scheduling algorithm, if a queue has any frame to transmit, it goes first. For RMAC ports, this is an easy way to provide the different service. For all recognizable traffic, the bandwidth is guaranteed to 100% of the line rate. This scheme works as long as the overall high priority bandwidth is not over the line rate and the latency on all the low priority traffic is don't care. The lowest priority queue is treated as "best effort" queue. The strict priority queue in the GMAC and CPU ports is similar to RMAC ports other than having 4 queues instead of 2 queues. The priority queue P0 can be scheduled only if the priority queue P1 is empty, so as to priority queues P2 and P3. Because we do not provide any assurances for "best effort" traffic, we do not enforce latency by dropping best effort traffic. Furthermore, because we assume that strict priority traffic is carefully controlled before entering the ZL50407, we do not enforce a fair bandwidth partition by dropping strict priority traffic. To summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. We only drop frames from best effort and strict priority queues when queue size is too long or global / class buffer resources become scarce.
39
Zarlink Semiconductor Inc.
ZL50407
7.2.2 Weighted Fair Queuing
Data Sheet
In some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, WFQ may be preferable to a strict assurance scheduling discipline. The ZL50407 provides this kind of scheduling algorithm on GMAC port only. The user sets four WFQ "weights" such that all weights are whole numbers and sum to 64. This provides per-class bandwidth partitioning with granular within 2%. In WFQ mode, though we do not assure frame latency, the ZL50407 still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control.
7.3
WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified parameters. The following table summarizes the behavior of the WRED logic. Px > WRED_L1 High Drop Low Drop X% Y% Px > WRED_L2 100% Z% BM Reject 100% 100%
Table 7 - WRED Logic Behaviour Px is the total byte count, in the priority queue x, can be the strict priority queue of RMAC ports and higher 3 priority queues for GMAC port. The WRED logic has two drop levels, depending on the value of Px. Each drop level has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. The X, Y Z percent can be programmed by the register RDRC0, RDRC1. All packets will be dropped only if the system runs out of the specific buffer resource, per class buffer or per source port buffer. The WRED thresholds of each queue can be programmed by the QOS control registers (refer to the register group 8). See Programming QoS Registers application note, ZLAN-42, for more information.
7.4
Shaper
Although traffic shaping is not a primary function of the ZL50407, the chip does implement a shaper for every queue in the GMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50407. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling. Traffic rate is set using a programmable whole number, no greater than 64. For example, if the setting is 32, then the traffic rate transmit out of the shaped queue is 32/64 * 1000 Mbps = 500 Mbps. See Programming QoS Register application note, ZLAN-42, for more information. Also, when shaping is enabled, it is possible for a queue to explode in length if fed by a greedy source. The reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. Though we do have global resource management, we do nothing other than per port WRED to prevent this situation locally. We assume the traffic is policed at a prior stage to the ZL50407 or WRED dropping is fine and shall restrain this situation.
7.5
Rate Control
The ZL50407 provides a rate control function on its RMAC ports. The concept is much the same as shaping, except that it applies to both ingress and egress directions and the control is per port rather than per queue. It provides a way of reducing the total bandwidth of all frames received from or transmitted to a port, to a rate below wire speed. As with shaping, the maximum burst size can also be configured. Rate control may be a valuable feature on RMAC ports in access applications where the service provider would like to limit the traffic received and transmitted by each port independently of each other, and independently of the
40
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
physical line rate. The service provider can then provide differential pricing, based on the negotiated bandwidth requirements for each user. In such applications of the ZL50407, the GMAC port is viewed as an uplink port, where rate control is not desired. See Rate Control application note, ZLAN-33, for more information.
7.6
Buffer Management
Because the number of FDB slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the ZL50407. Our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in Figure 9 on page 41. As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the frame first enters the ZL50407, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. Three priority sections, one for each pair of the first six priority classes, ensure a programmable number of FDB slots per class. The lowest two classes do not receive any buffer reservation. Furthermore, a frame is stored in the region of the FDB corresponding to its class. As we have indicated, the eight classes use only two transmission scheduling queues for RMAC ports (four queues for the GMAC & CPU ports), but as far as buffer usage is concerned, there are still eight distinguishable classes. Another segment of the FDB reserves space for each of the 10 ports -- 9 ports for Ethernet and one CPU port (port number 8). Each port has it's own programmable source port reservation. These 10 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. In addition, there is a shared pool, which can store any type of frame. The frame engine allocates the frames first in the three priority sections. When the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared pool. Once the shared pool is full the frames are allocated in the section reserved for the source port. The following registers define the size of each section of the Frame data Buffer: PR100_N - Port Reservation for RMAC Ports PR100_CPU - Port Reservation for CPU Port PRG - Port Reservation for GMAC Port SFCB - Share FCB Size C1RS - Class 1 Reserve Size (priority 2 & 3) C2RS - Class 2 Reserve Size (priority 4 & 5) C3RS - Class 3 Reserve Size (priority 6 & 7)
Temporary reservation
Per Class Reservation Per Source Port Reservation
Rpri1
Rpri2
Rpri3
Shared Pool S
Rp0
Rp1
Rp2
Rp3
Rp4
Rp5
Rp6
Rp7
Rp8
(CPU)
Rp9
Figure 9 - Buffer Partition Scheme
41
Zarlink Semiconductor Inc.
ZL50407
See Buffer Allocation application note, ZLAN-47, for more information.
Data Sheet
7.6.1
Dropping When Buffers Are Scarce
As already discussed, the WRED mechanism may drop frames on output queue status. In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible. If a received frame is dispatched to the P0 ("best effort") queue, the buffer management will check on the overall buffer situation plus the output queue status to decide the frame drop condition. If the source port has not enough buffer for it, the frame will be dropped. If the output queue reaches PCC (packet congest control) and the shared buffer has run out, the frame may be dropped by RED (at B%). If the output queue reaches PCC and the source port reservation is lower than the buffer low threshold, the frame will be dropped. For multicast frames, global thresholds are used to manage scarce resources. When a multicast frame is received, the buffer management will check on the overall buffer situation. If total multicast resources reaches MCCTH (multicast congest control threshold), the frame may be dropped by RED (at B%). If total multicast resources reaches MCC, the frame will be dropped. All the 100% dropping functions are disabled if the source port is flow control capable, however, RED (at B%) will still be applied.
7.7
Flow Control Basics
Because frame loss is unacceptable for some applications, the ZL50407 provides a flow control option. When flow control is enabled, scarcity of source port buffer space may trigger a flow control signal; this signal tells a source port sending a packet to this switch, to temporarily hold off. While flow control offers the clear benefit of no packet loss, it also introduces a problem for quality of service. When a source port receives an Ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. A single packet destined for a congested output can block other packets destined for un-congested outputs. The resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. On the other hand, the ZL50407 will still prioritize the received frame disregarding the outgoing port flow control capability. If a frame is classified as high priority, it is still subjected to the WRED, which means the no-loss on the high priority queue is not guaranteed. To resolve this situation, the user may set the output port WRED threshold so high that may never be reached, or program the priority mapping table in the queue manager to map all the traffic to "best effort" (P0) queue on the flow control capable port. The first method has side impact on the global resource management since the port may hold too much per class resource that is scarce in the system. The second method, by nature, lost the benefit of prioritization. See Programming Flow Control Registers application note, ZLAN-44, for more information.
7.7.1
Unicast Flow Control
For unicast frames, flow control is triggered by source port resource availability. Recall that the ZL50407's buffer management scheme allocates a reserved number of FDB slots for each source port. If a programmed number of a source port's reserved FDB slots have been used, then flow control Xoff is triggered. Xon is triggered when a port is currently being flow controlled, and all of that port's reserved FDB slots have been released. Note that the ZL50407's per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled.
42
Zarlink Semiconductor Inc.
ZL50407
7.7.2 Multicast Flow Control
Data Sheet
Flow control for multicast frames is triggered by a global buffer counter. When the system exceeds a programmable threshold of multicast packets, Xoff is triggered. Xon is triggered when the system returns below this threshold. Note: If per-port flow control is on, QoS performance will be affected.
7.8
Mapping to IETF Diffserv Classes
The mapping between priority classes discussed in this chapter and elsewhere is shown below. ZL50407 IETF P3 NM+EF P2 AF0 P1 AF1 P0 BE
Table 8 - Mapping to IETF Diffserv Classes for GMAC & CPU Ports As the table illustrates, the classes of Table 8 are merged in pairs-- P3 is used for network management (NM) and expedited forwarding service (EF) frames. Classes P2 and P1 correspond to an assured forwarding (AF) group of size 2. Finally, P0 is for best effort (BE) class. Features of the ZL50407 that correspond to the requirements of their associated IETF classes are summarized in the table below. Network management (NM) and Expedited forwarding (EF) Assured forwarding (AF) Global buffer reservation for NM and EF Shaper for traffic on uplink port No dropping if admission controlled Global buffer reservation for two AF classes Shaper for traffic on uplink port Random early discard, with programmable levels Service only when other queues are idle means that QoS not adversely affected Shaper for traffic on uplink port Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified as BE Table 9 - ZL50407 Features Enabling IETF Diffserv Standards
Best effort (BE)
7.9
Failover Backplane Feature
The ZL50407 implements a hardware assisted link failure detection mechanism utilizing a Link Heart Beat (LHB) packet. The LHB packet format is defined as a 64-byte MAC control frame with a user defined opcode. The packet format is illustrated below: 01-80-C2-00-00-01 xx-xx-xx-xx-xx-xx 88-08 yy-yy 00-00-... CRC
Where "xx-xx-xx-xx-xx-xx" is the source port MAC address and "yy-yy" is the special opcode defined by register setup (LHBReg0,1). The opcode "00-01" is reserved for the flow control packet. We recommend opcode "00-12" for the LHB packet. The LHB is done between two compatible MACs providing this function. A timer parameter will be set for both the receiver and transmitter (LHBTimer).
43
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
On the transmission side, the MAC will monitor the transmission activities. If there is no activity for more than the set period, a LHB packet will be sent to its link partner. Therefore, there should always be at least one packet transmitted from the MAC for every period specified. On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50407 to reset the timeout counter, it is ignored otherwise (i.e. not passed on within the system). See the Failover Protection Application Note, ZLAN-43, for more information.
8.0
Port Trunking
See Port Trunking application note, ZLAN-48, for more information.
8.1
Features and Restrictions
A port group (i.e., trunk) can include up to 8 physical ports, all of the ports in a group can be in the same ZL50407 or in multiple ZL50407 to form a fault tolerant link. There are eight trunk groups total. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address. Three other options include source MAC address only, destination MAC address only, and source port (in bidirectional ring mode only). Load distribution for multicast is performed similarly. If a VLAN includes any of the ports in a trunk group, all the ports in that trunk group should be in the same VLAN member map. The ZL50407 also provides a safe fail-over mode for port trunking automatically. If one of the ports in the trunking group goes down, the ZL50407 can redistribute the traffic over to the remaining ports in the trunk with software assistance.
8.2
Unicast Packet Forwarding
The search engine finds the destination MCT entry, and if the status field says that the destination port found belongs to a trunk, then the trunk group number is retrieved. The source port of the packet is checked against the destination trunk group. If the source port belongs to the destination trunk group, the packet is discarded. A hash key, based on some combination of the source and destination MAC addresses for the current packet, selects the appropriate forwarding port, as specified in the Trunk_Hash registers. Each trunk has eight trunk_hash registers which selects one of the potential eight outgoing ports. The hash key provides a pseudo flow identifier which force the same flow to the same destination flow. As a result, the packet will always arrive in order.
8.3
Multicast Packet Forwarding
Multicast frame forwarding is only slightly more complex than unicast frame forwarding in a port trunking environment: 1. Determine the VLAN to which the multicast frame belongs. 2. Is the frame's source port a member of the VLAN? If so, exclude that port. Is the frame's source port a member of a trunk group? If so, exclude all other ports in that group as well. 3. Finally, among the still-eligible members of the VLAN that belong to trunk groups, exclude all but one port from each trunk group. This selection is based on hashing or round robin, as in unicast frame forwarding. Example: Ports 0, 1, and 2 belong to trunk group A. Ports 3 and 4 belong to trunk group B. A multicast frame is received from source port 3. Suppose that the VLAN of the frame has member ports 0, 1, 2, 3, 4, 5, and 6. * * Ports 0, 1, 2, 3, 4, 5, and 6 are potential destination ports for the frame. Port 3 is excluded as a destination because it is the frame's source port.
44
Zarlink Semiconductor Inc.
ZL50407
* * *
Data Sheet
Port 4 is excluded as a destination because it belongs to the same trunk group as port 3. Two of the three ports in trunk group A must now be excluded. The ZL330ENG hashing algorithm is applied, and in this example, assume that ports 0 and 1 are excluded. Therefore, ports 2, 5 and 6 comprise the final set of destination ports for the multicast frame.
9.0
Traffic Mirroring
See Traffic Mirroring application note, ZLAN-50, for more information.
9.1
Mirroring Features
Packets can be mirrored (duplicated) for network monitor purpose and/or network debug purpose. Three types of mirroring is available in ZL50407. 1. Source or Destination MAC address based 2. Flow based 3. Port based (RMII mode only) In source or destination mac address based mirroring, the "M" bit of the mirroring MAC address in the MCT is set. Also, the user need to specify the mirroring MAC address is source or destination of the packet. If source is selected, any packet received with the mirroring MAC address as source MAC address will be copied to the mirrored port. In the same way, if destination is selected, any packet received with mirroring MAC address as destination MAC address will be copied to the mirrored port. In flow based mirroring, a flow is established based on the source and destination mac address pair. When enabled, a packet with source and destination address match the pre-programmed source and destination mac address pair will be copied to the mirrored port. In reverse direction (source and destination match pre programmed destination and source), the flow can also be enabled and the frame will be copied to the mirrored port. In port based mirroring, traffic from any RMII port can be mirrored to any other RMII port. The traffic from the source port can be either ingress or egress traffic. Up to two ports can be setup as mirrored ports. As a result, the traffic (both ingress and egress) of a specific port can be monitored by setting up both mirrored ports. Once a port is setup as mirrored port, it cannot be used for regular traffic. The mirrored port can be any port in the ZL50407.
9.2
Using port mirroring for loop back
To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check the data path. The CPU needs to setup the remote device through the command channel to enable port mirroring in the remote device. A CPU packet is send to the port in test in Device A. The packet will be forwarded to the test port, external cable, the destination port in Device B, and loop back to itself, back to the cable and go back to Device A and the CPU. This way, the whole channel can be tested.
CPU
DEVICE A
DEVICE B
Figure 10 - Remote Loopback Test
45
Zarlink Semiconductor Inc.
ZL50407 10.0
10.1 10.1.1
Data Sheet
Clocks
Clock Requirements System Clock (SCLK) Speed Requirement
SCLK is the primary clock for the ZL50407 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Minimum SCLK speed required 100 MHz 50 MHz 25 Mhz Table 10 - SCLK Speed Requirements
Configuration 8 Port 10/100M + 1 port 1000M 6-9 ports 10/100 M 1-5 ports 10/100 M
10.1.2
RMAC Reference Clock (M_CLK) Speed Requirement
M_CLK is a 50 MHz clock used for the RMAC ports (ports 0-7). If none of the RMAC ports are configured in RMII mode or Reverse MII mode, a different clock frequency can be applied to M_CLK, as long as it's less than 50 MHz. In this case, register USD must be set to provide an internal 1usec timing.
10.1.3
GMAC Reference Clock (GREF_CLK) Speed Requirement
GREF_CLK is a 125 MHz reference clock required for the GMAC port (port 9). If the device is in a 9 port 10/100 configuration only, GREF_CLK can be a lower frequency clock and can be connected to M_CLK to reduce the number of clock sources. If port 9 is not being used, GREF_CLK can be left unconnected.
10.1.4
JTAG Test Clock (TCK) Speed Requirements
TCK is a clock used for the JTAG port. The frequency on this clock can vary. Refer to "JTAG (IEEE 1149.1-2001)" on page 131 for the frequency range.
10.2 10.2.1
Clock Generation MDC
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50 MHz is used on M_CLK, the USD register must be programmed to reset MDC.
10.2.2
SCL
SCL is used for the I2C interface and clocks data on SDA. It is generated by the device from M_CLK and is equal to 50kHz (M_CLK/1000). If a different speed clock other than 50 MHz is used on M_CLK, the USD register must be programmed to reset SCL.
46
Zarlink Semiconductor Inc.
ZL50407
10.2.3 Ethernet Interface Clocks
Data Sheet
If the RMAC ports are configured in Reverse MII mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for 100 M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50 MHz clock in this mode. If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for 10 M mode. M_CLK needs to be a 20 MHz clock in this mode and USD must be programmed accordingly. The gigabit port generates an external TXCLK interface clock in GMII mode. It is equal to the 125 MHz GREF_CLK. If the GMAC port is configured in Reverse MII mode, RXCLK is generated from GREF_CLK and is equal to GREF_CLK/2 for 100 M mode (no support for 10M Reverse MII mode). GREF_CLK needs to be a 50 MHz clock in this mode.
11.0
11.1
Hardware Statistics Counters
Hardware Statistics Counters List
ZL50407 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the filtering counter (detected by queue manager). The following is the wrapped signal sent to the CPU through the command block. See Processor Interface application note, ZLAN-26, for more information.
11.2 11.2.1
IEEE 802.3 HUB Management (RFC 1516) Event Counters PortReadableFrames
11.2.1.1
Counts the number of frames of valid frame length that have been received on this port. Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) No FCS (i.e. checksum) error No collisions Use ZL50407 counter "Total Frames Received", C[8]. Note: max. frame size may be BUF_LIMIT, if enabled on this port.
11.2.1.2
PortReadableOctets
Counts the number of bytes (i.e. octets) contained in valid frames that have been received on this port.
47
Zarlink Semiconductor Inc.
ZL50407
Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) No FCS error No collisions Use ZL50407 counter "Total Bytes Received", C[7]. Note: max. frame size may be BUF_LIMIT, if enabled on this port.
Data Sheet
11.2.1.3
PortFCSErrors
Counts number of valid frames received with bad FCS. Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) No framing error No collisions Use ZL50407 counter "CRC", C[23]. Note: if BUF_LIMIT is enabled on this port, this counter still uses the above max. frame size definition. If a frame >1518B but 11.2.1.4
PortAlignmentErrors
Counts number of valid frames received with bad alignment (not byte-aligned). Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) Framing error FCS error No collisions Use ZL50407 counter "Alignment Error", C[21]. Note: when this counter is incremented, the ZL50407 also increments the "CRC" counter, C[23].
48
Zarlink Semiconductor Inc.
ZL50407
11.2.1.5 PortFrameTooLongs
Data Sheet
Counts number of frames received with size exceeding the maximum allowable frame size. Min. Frame Size Frame size: n/a Max. Frame Size > 1518 bytes (> 1522 bytes, if VLAN tagged) Framing error: don't care FCS error: don't care No collisions Use ZL50407 counter "Oversize Frames", C[15]. Note: max. frame size may be BUF_LIMIT, if enabled on this port. Also, if a frame >1518B but 11.2.1.6
PortShortEvents
Counts number of frames received with size less than the length of a short event. Min. Frame Size Frame size: < 10 bytes Max. Frame Size
Framing error: don't care FCS error: don't care No collisions Use ZL50407 counter "Short Event", C[24].
11.2.1.7
PortRunts
Counts number of frames received with size under 64 bytes, but greater than the length of a short event. Min. Frame Size Frame size: > 10 bytes, Max. Frame Size < 64 bytes
Framing error: don't care FCS error: don't care No collisions Use ZL50407 counter "Undersize Frames", C[22].
49
Zarlink Semiconductor Inc.
ZL50407
11.2.1.8 PortCollisions
Data Sheet
Counts number of collision events. Min. Frame Size Frame size: Use ZL50407 counter "Collision", C[25]. Max. Frame Size
any size
11.2.1.9
PortLateEvents
Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Min. Frame Size Frame size: Use ZL50407 counter "Port Late Collision", C[29]. Note: when this counter is incremented, the ZL50407 also increments the "Collision" counter, C[25]. Max. Frame Size
any size
11.2.1.10
PortVeryLongEvents
Counts number of frames received with size larger than Jabber Lockup Protection Timer (TW3 = 5 ms or 50 000 bit times - 20% + 50%). Min. Frame Size Frame size: No ZL50407 counter. Note: the ZL50407 defines a jabber frame as any frame that exceeds 6400 bytes, however, the maximum buffer size supported by the device is 4 KBytes. Thus, any frame > 4KB would be counted as an Oversized Frame, C[15]. > TW3 Max. Frame Size
11.2.1.11
PortDataRateMisatches
For repeaters or HUB application only. No ZL50407 counter.
11.2.1.12
PortAutoPartitions
For repeaters or HUB application only. No ZL50407 counter.
11.2.1.13
PortTotalErrors
Sum of the following errors: * * * * * * * PortFCSErrors PortAlignmentErrors PortFrameTooLong PortShortEvents PortLateEvents PortVeryLongEvents PortDataRateMisatches
50
Zarlink Semiconductor Inc.
ZL50407
11.3 11.3.1 11.3.1.1 IEEE 802.1 Bridge Management (RFC 1286) Event Counters PortDelayExceededDiscards
Data Sheet
Counts number of frames discarded due to excessive transmit delay through the bridge. Note: Not applicable for the ZL50407.
11.3.1.2
PortMtuExceededDiscards
Counts number of frames discarded due to excessive size.
11.3.1.3
PortInFrames
Counts number of frames received by this port or segment. Note: A frame received by this port is only counted by this counter if and only if it is for a protocol being processed by the local bridge function.
11.3.1.4
PortOutFrames
Counts number of frames transmitted by this port. Note: A frame transmitted by this port is only counted by this counter if and only if it is for a protocol being processed by the local bridge function.
11.3.1.5
PortInDiscards
Counts number of valid frames received which were discarded (i.e. filtered) by the forwarding process.
11.4 11.4.1
RMON - Ethernet Statistic Group (RFC 1757) Event Counters DropEvents
11.4.1.1
Counts number of times a packet is dropped, because of lack of available resources. DOES NOT include all packet dropping -- for example, random early drop for quality of service support. Use ZL50407 counter "Drop", C[26].
11.4.1.2
Octets
Counts the total number of octets (i.e. bytes) in any frames received. Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) No framing error FCS error: don't care No collisions
51
Zarlink Semiconductor Inc.
ZL50407
Use ZL50407 counter "Bytes Received", C[5]. Note: max. frame size may be BUF_LIMIT, if enabled on this port.
Data Sheet
11.4.1.3
Pkts
Counts the number of frames received, good or bad. Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) No framing error FCS error: don't care No collisions Use ZL50407 counter "Frames Received", C[6]. Note: max. frame size may be BUF_LIMIT, if enabled on this port.
11.4.1.4
BroadcastPkts
Counts the number of good frames received and forwarded with broadcast address. Does not include non-broadcast multicast frames. Use ZL50407 counter "Broadcast Frames Received", C[11].
11.4.1.5
MulticastPkts
Counts the number of good frames received and forwarded with multicast address. Does not include broadcast frames. Use ZL50407 counter "Multicast Frames Received", C[10]. Note: this counter includes broadcast frames received.
11.4.1.6
CRCAlignErrors
Counts number of frames received with FCS or alignment errors. Min. Frame Size Frame size: > 64 bytes, Max. Frame Size < 1518 bytes (< 1522 bytes, if VLAN tagged) Framing error and/or FCS error No collisions Use ZL50407 counters "CRC", C[23], and "Alignment Error", C[21]. Note: when the "Alignment Error" counter, C[21], is incremented, the ZL50407 also increments the "CRC" counter, C[23], thus, the CRC counter can be used for this statistic.
52
Zarlink Semiconductor Inc.
ZL50407
11.4.1.7 UndersizePkts
Data Sheet
Counts number of frames received with size less than 64 bytes. Min. Frame Size Frame size: n/a Max. Frame Size < 64 bytes
Framing error: don't care FCS error: don't care No collisions Use ZL50407 counter "Undersize Frames", C[22].
11.4.1.8
OversizePkts
Counts number of frames received with size exceeding the maximum allowable frame size. Min. Frame Size Frame size: n/a Max. Frame Size > 1518 bytes (> 1522 bytes, if VLAN tagged) Framing error: don't care FCS error: don't care No collisions Use ZL50407 counter "Oversize Frames", C[15]. Note: max. frame size may be BUF_LIMIT, if enabled on this port.
11.4.1.9
Fragments
Counts number of frames received with size less than 64 bytes and with bad FCS. Min. Frame Size Frame size: n/a Max. Frame Size < 64 bytes
Framing error and/or FCS error No collisions Use ZL50407 counter "Fragments", C[20].
53
Zarlink Semiconductor Inc.
ZL50407
11.4.1.10 Jabbers
Data Sheet
Counts number of frames received with size exceeding maximum frame size and with bad FCS. Note that this definition of jabber is different than the definition in IEEE 802.3 (this standard defines jabber as the condition where any packet exceeds Jabber Lockup Protection Timer (TW3)). Min. Frame Size Frame size: n/a Max. Frame Size > 1518 bytes (> 1522 bytes, if VLAN tagged) Framing error: don't care FCS error No collisions No ZL50407 counter. Note: the ZL50407 defines a jabber frame as any frame that exceeds 6400 bytes, however, the maximum buffer size supported by the device is 4 KBytes. Thus, any frame > 4 KB would be counted as an Oversized Frame, C[15].
11.4.1.11
Collisions
Counts number of collision events detected. Only a best estimate since collisions can only be detected while in transmit mode, but not while in receive mode. Min. Frame Size Frame size: Use ZL50407 counter "Collision", C[25]. Max. Frame Size
any size
54
Zarlink Semiconductor Inc.
ZL50407
11.4.1.12 Packet Count for Different Size Groups
Data Sheet
Six different size groups - one counter for each. Counts both good and bad packets. Pkts64Octets for any packet with size = 64 bytes. Use ZL50407 counter "Frames with Length of 64 Bytes", C[12]. Pkts65to127Octets for any packet with size from 65 bytes to 127 bytes Use ZL50407 counter "Frames with Length Between 65-127 Bytes", C[14]. Pkts128to255Octets or any packet with size from 128 bytes to 255 bytes Use ZL50407 counter "Frames with Length Between 128-255 Bytes", C[16]. Pkts256to511Octets for any packet with size from 256 bytes to 511 bytes Use ZL50407 counter "Frames with Length Between 256-511 Bytes", C[17]. Pkts512to1023Octets for any packet with size from 512 bytes to 1023 bytes Use ZL50407 counter "Frames with Length Between 512-1023 Bytes", C[18]. Pkts1024to1518Octets for any packet with size from 1024 bytes to 1518 bytes Use ZL50407 counter "Frames with Length Between 1024-1518 Bytes", C[19]. Note: the ZL50407 will include frames up to max. frame size. Note: the ZL50407 doesn't include bad frames in the above counters.
11.5
Miscellaneous Counters
In addition to the statistics groups defined in previous sections, the ZL50407 has other statistics counters for its own purposes. 1. Flow control - one counting the number of flow control frames received, C[9], and another counting the number of flow control frames sent, C[3]. 2. Frames sent - one for unicast frames sent, C[1], and one for non-unicast frames sent, C[4]. A broadcast or multicast frame qualifies as non-unicast. 3. A counter called "frame send fail", C[2]. This keeps track of FIFO under-runs, late collisions, and collisions that have occurred 16 times. 4. A counter called "filtering", C[27]. This keeps track of all frames dropped due to queue congestion (i.e. egress WRED).
55
Zarlink Semiconductor Inc.
ZL50407 12.0
12.1
Data Sheet
Register Definition
ZL50407 Register Description
CPU Addr (Hex) IC Addr (Hex) Default (Hex)
Register
Description
R/W
Notes
0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9)) ECR1Pn ECR2Pn ECR3Pn ECR4Pn BUF_LIMIT FCC AVTCL AVTCH PVMAPn_0 PVMAPn_1 PVMAPn_3 PVMODE TRUNKn TRUNKn_HASH10 TRUNKn_HASH32 TRUNKn_HASH54 TRUNKn_HASH76 MULTICAST_HASHn-0 Port Control Register 1 for Port n Port Control Register 2 for Port n Port Control Register 3 for Port n Port Control Register 4 for Port n Frame Buffer Limit Flow Control Grant Period VLAN Type Code Register Low VLAN Type Code Register High Port n Configuration Register 0 Port n Configuration Register 1 Port n Configuration Register 3 VLAN Operating Mode Trunk Group n Trunk Group n Hash 10 Destination Port Trunk Group n Hash 32 Destination Port Trunk Group n Hash 54 Destination Port Trunk Group n Hash 76 Destination Port Multicast hash result n mask byte 0 0000+2n 0001+2n 0080+2n 0081+2n 0036 0037 0100 0101 0102+4n 0103+4n 0105+4n 0170 0200+n 0208+4n 0209+4n 020A+4n 020B+4n 0228+2n R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 000+n 00A+n 014+n 01E+n NA NA 028 029 02A+n 034+n 03E+n 048 NA NA NA NA NA NA C0 00 00 18 40 03 00 81 FF FF 00 00 00 00 00 00 00 FF
1. VLAN Control Registers (Substitute [n] with Port number (0..9))
2. TRUNK Control Registers (Substitute [n] with Trunk Group number (0..7))
Table 11 - Register Description
56
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex) NA
Data Sheet
Register MULTICAST_HASHn-1 3. CPU Port Configuration MAC0 MAC1 MAC2 MAC3 MAC4 MAC5 INT_MASK0 INTP_MASKn RQS RQSS MAC01 MAC23 MAC45 MAC67 MAC9 CPUQINS[6:0] CPUQINSRPT CPUGRNHDL[1:0] CPURLSINFO[4:0] CPUGRNCTR 4. Search Engine Configurations AGETIME_LOW AGETIME_HIGH SE_OPMODE 5. Global QOS Control QOSC
Description Multicast hash result n mask byte 1 CPU MAC Address byte 0 CPU MAC Address byte 1 CPU MAC Address byte 2 CPU MAC Address byte 3 CPU MAC Address byte 4 CPU MAC Address byte 5 Interrupt Mask 0 Interrupt Mask for MAC Port 2n, 2n+1 Receive Queue Select Receive Queue Status Increment MAC port 0,1 address Increment MAC port 2,3 address Increment MAC port 4,5 address Increment MAC port 6,7 address Port 9 MAC address byte 5
CPU Addr (Hex) 0229+2n
R/W R/W
Default (Hex) FF
Notes
0300 0301 0302 0303 0304 0305 0306 0310+n 0323 0324 0325 0326 0327 0328 0329 0330-0336 0337 0338-0339 033A-033E 033F
R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 049 04A NA
00 00 00 00 00 00 00 00 00 NA 00 00 00 00 00 00 NA NA 00 00 5C 00 00 (n=0..4)
MAC Address Aging Time Low MAC Address Aging Time High Search Engine Operating Mode QOS Control
0400 0401 0403
0500
R/W
04B
00
Table 11 - Register Description (continued)
57
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex) 068 069 NA 090 091 NA 074 075 076 077 056 057 058 05C 059 05A 05B 05D 0B3+n 0BB 0A8 0A9 0AA 0AB 0AC 0AD
Data Sheet
Register PCC MCC MCCTH RDRC0 RDRC1 RDRC2 SFCB C1RS C2RS C3RS AVPML AVPMM AVPMH AVDM TOSPML TOSPMM TOSPMH TOSDML USER_PROTOCOL_n USER_PROTOCOL_ FORCE_DISCARD WLPP10 WLPP32 WLPP54 WLPP76 WLPE WLPFD
Description Packet Congestion Control Multicast Congestion Control Multicast Congestion Threshold WRED Drop Rate Control 0 WRED Drop Rate Control 1 WRED Drop Rate Control 2 Share FCB Size Class 1 Reserve Size Class 2 Reserve Size Class 3 Reserve Size VLAN Priority Map Low VLAN Priority Map Middle VLAN Priority Map High VLAN Discard Map TOS Priority Map Low TOS Priority Map Middle TOS Priority Map High TOS Discard Map User Define Protocol n User Define Protocol 0 To 7 Force Discard Enable Well Known Logic Port 0 and 1 Priority Well Known Logic Port 2 and 3 Priority Well Known Logic Port 4 and 5 Priority Well Known Logic Port 6 and 7 Priority Well Known Logic Port 0 To 7 Enable Well Known Logic Port 0 To 7 Force Discard Enable
CPU Addr (Hex) 0510 0511 0512 0513 0514 0515 0518 0519 051A 051B 0530 0531 0532 0533 0540 0541 0542 0543 0550+n 0558 0560 0561 0562 0563 0564 0565
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default (Hex) 006 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Notes
(n=0..7)
Table 11 - Register Description (continued)
58
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex) 092+n 09A+n 0A2 0A3 0A4 0A5 0A6 0A7 0AE 0AF 0B0 0B1 0B2 0BC 0BD 0BE NA NA NA NA NA NA NA NA
Data Sheet
Register USER_PORTn_LOW USER_PORTn_HIGH USER_PORT1:0_ PRIORITY USER_PORT3:2_ PRIORITY USER_PORT5:4_ PRIORITY USER_PORT7:6_ PRI ORITY USER_PORT_ ENABLE[7:0] USER_PORT_ FORCE_DISCARD[7:0] RLOWL RLOWH RHIGHL RHIGHH RPRIORITY MII_OP0 MII_OP1 FEN MIIC0 MIIC1 MIIC2 MIIC3 MIID0 MIID1 USD DEVICE
Description User Define Logical Port n Low User Define Logical Port n High User Define Logic Port 0 and 1 Priority User Define Logic Port 2 and 3 Priority User Define Logic Port 4 and 5 Priority User Define Logic Port 6 and 7 Priority User Define Logic Port 0 To 7 Enable User Define Logic Port 0 To 7 Force Discard Enable User Define Range Low Bit [7:0] User Define Range Low Bit [15:8] User Define Range High Bit [7:0] User Define Range High Bit [15:8] User Define Range Priority MII Register Option 0 MII Register Option 1 Feature Registers MII Command Register 0 MII Command Register 1 MII Command Register 2 MII Command Register 3 MII Data Register 0 MII Data Register 1 One micro second divider Device id and test
CPU Addr (Hex) 0570+2n 0571+2n 0590 0591 0592 0593 0594 0595 05A0 05A1 05A2 05A3 05A4 0600 0601 0602 0603 0604 0605 0606 0607 0608 0609 060A
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W
Default (Hex) 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 NA NA 00 02
Notes (n=0..7)
6. MISC Configuration Register
Table 11 - Register Description (continued)
59
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex) 0FF NA NA NA NA NA 0BF 0C0 0C1
Data Sheet
Register SUM LHBTimer LHBReg0 LHBReg1 fMACCReg0 fMACCReg1 FCB_BASE_ADDR0 FCB_BASE_ADDR1 FCB_BASE_ADDR2 7. Port Mirroring Controls MIRROR_DEST_MAC0 MIRROR_DEST_MAC1 MIRROR_DEST_MAC2 MIRROR_DEST_MAC3 MIRROR_DEST_MAC4 MIRROR_DEST_MAC5 MIRROR_SRC_MAC0 MIRROR_SRC_MAC1 MIRROR_SRC_MAC2 MIRROR_SRC_MAC3 MIRROR_SRC_MAC4
Description EEPROM Checksum Register Link heart beat time out timer LHB control field value[7:0] LHB control field value [15:8] Forced MAC control field value [7:0] Forced MAC control field value [15:8] FCB Base Address Register 0 FCB Base Address Register 1 FCB Base Address Register 2 Mirror Destination MAC Address 0 Mirror Destination MAC Address 1 Mirror Destination MAC Address 2 Mirror Destination MAC Address 3 Mirror Destination MAC Address 4 Mirror Destination MAC Address 5 Mirror Source MAC Address 0 Mirror Source MAC Address 1 Mirror Source MAC Address 2 Mirror Source MAC Address 3 Mirror Source MAC Address 4
CPU Addr (Hex) 060B 0610 0611 0612 0613 0614 0620 0621 0622
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default (Hex) 00 00 00 00 00 00 00 60 00
Notes
0700 0701 0702 0703 0704 0705 0706 0707 0708 0709 070A
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
NA NA NA NA NA NA NA NA NA NA NA
00 00 00 00 00 00 00 00 00 00 00
Table 11 - Register Description (continued)
60
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex) NA NA NA NA 04C+n 05E+n 06A+n
Data Sheet
Register MIRROR_SRC_MAC5 MIRROR_CONTROL RMII_MIRROR0 RMII_MIRROR1 8. Per Port QOS Control FCRn BMRCn PR100_n
Description Mirror Source MAC Address 5 Port Mirror Control Register RMII Mirror 0 RMII Mirror 1 Flooding Control Register n Broadcast/Multicast Rate Control n Port Reservation for RMAC Ports (n=0..7)
CPU Addr (Hex) 070B 070C 0710 0711 0800+n 0820+n 0840+n
R/W R/W R/W R/W R/W R/W R/W R/W
Default (Hex) 00 00 00 00 00 00 06
Notes
(n=0..9)
`d1536/1 6=`d96, `d96>>4= 'h6 `d96 `d96x6=`d 576, `d576>>4 ='h24 1/2 1/2 1/2 (n=0..39)
PR100_CPU PRG
Port Reservation for CPU Port Port Reservation for GMAC Port
0848 0849
R/W R/W
073 072
06 24
PTH100_n PTH100_CPU PTHG QOSCn E. System Diagnostic DTSRL DTSRM TESTOUT0 TESTOUT1 MASK0 MASK1 MASK2 MASK3 MASK4
Port Threshold for RMAC Ports (n=0..7) Port Threshold for CPU Port Port Threshold for GMAC Port QOS Control n
0860+n 0868 0869 0880+n
R/W R/W R/W R/W
0C2+n 0CB 0CA 078-08F NA
03 03 12 00
Test Register Low Test Register Medium Testmux Output [7:0] Testmux Output [15:8] MASK Timeout 0 MASK Timeout 1 MASK Timeout 2 MASK Timeout 3 MASK Timeout 4
0E00 0E01 0E02 0E03 0E10 0E11 0E12 0E13 0E14
R/W R/W R/O R/O R/W R/W R/W R/W R/W
NA NA NA NA 0F6 0F7 0F8 0F9 0FA
00 01 NA NA 00 00 00 00 00
Table 11 - Register Description (continued)
61
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex) NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Data Sheet
Register BOOTSTRAP[2:0] PRTFSMSTn PRTQOSSTn PRTQOSST8A PRTQOSST8B PRTQOSST9A PRTQUSST9B CLASSQOSST PRTINTCTR QMCTRLn QCTRL BMBISTR0 BMBISTR1 BMControl BUFF_RST FCBHEADPTR0 FCB_HEAD_PTR1 FCB_TAIL_PTR0 FCB_TAIL_PTR1 FCB_NUM0 FCB_NUM1 BM_RLSFF_CTRL BM_RLSFF_INFO0 BM_RLSFF_INFO1 BM_RLSFF_INFO2 BM_RLSFF_INFO3 BM_RLSFF_INFO4 BM_RLSFF_INFO5
Description BOOTSTRAP Read Back Ethernet Port n Status Read Back RMAC Port n QOS and Queue Status CPU Port QOS and Queue Status A CPU Port QOS and Queue Status B GMAC Port QOS and Queue Status A GMAC Port QOS and Queue Status B Class Buffer Status Buffer Interrupt Status Ports Queue Control Status Ports Queue Control Memory bist result Memory bist result Memory control Buffer Reset Pool FCB Head Pointer [7:0] FCB Head Pointer [15:8] FCB Tail Pointer [7:0] FCB Tail Pointer [15:8] FCB Number [7:0] FCB Init Start and FCB Number [14:8] Read control register Bm_rlsfifo_info[7:0] Bm_rlsfifo_info[15:8] Bm_rlsfifo_info[23:16] Bm_rlsfifo_info[31:24] Bm_rlsfifo_info[39:32] Fifo_cnt[2:0],Bm_rlsfifo_inf o[44:40]
CPU Addr (Hex) 0E80-0E82 0E90+n 0EA0+n 0EA8 0EA9 0EAA 0EAB 0EAC 0EAD 0EB0+n 0EBA 0EBB 0EBC 0EBD 0EC0 0EC1 0EC2 0EC3 0EC4 0EC5 0EC6 0EC7 0EC8 0EC9 0ECA 0ECB 0ECC 0ECD
R/W RO RO RO RO RO RO RO RO R/W R/W R/W R/O R/O R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO
Default (Hex) NA NA NA NA NA NA NA NA 00 00 00 NA NA 0F 00 00 00 00 00 00 06 00 NA NA NA NA NA NA
Notes
(n=0..9) (n=0..7)
(n=0..9)
Table 11 - Register Description (continued)
62
Zarlink Semiconductor Inc.
ZL50407
IC Addr (Hex)
Data Sheet
Register F. System Control GCR DCR DCR1 DPST DTST DA
Description
CPU Addr (Hex)
R/W
Default (Hex)
Notes
Global Control Register Device Control Register Device Control Register 1 Device Port Status Register Data read back register DA Register
0F00 0F01 0F02 0F03 0F04 0FFF
R/W RO RO R/W RO RO
NA NA NA NA NA NA
00 NA NA 00 NA DA
Table 11 - Register Description (continued)
12.2
Directly Accessed Registers
Width 16-bit Default: 00 Access W Address 0
INDEX_REG
Used to write the address of the indirect register to be accessed.
Bit # [15:0]
Name INDEX
Type W
Description 16-bit address of the indirect register
Register Table 1 - 0, INDEX_REG
DATA_REG
Reflects the value of the indirect access register set by INDEX_REG
Width 8-bit Default: 00
Access R/W
Address 2
Bit # [7:0]
Name DATA
Type R/W
Description 8-bit indirect register data
Register Table 2 - 2, DATA_REG
63
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
CPU_FRAME_REG
Used to transmit/receive Ethernet frames via an 8-byte FIFO to/from the CPU MAC. This register (FIFO) is disabled in SSI+MII CPU interface mode.
Width 16-bit Default: 00
Access R/W
Address 3
Bit # [15:0]
Name CPU_FRAME
Type W
Description Send Ethernet frame to CPU MAC. Bits [7:0] is even byte, [15:8] is odd byte. Data sequence specified in Processor Interface application note, ZLAN-26.
R
Receive Ethernet frame from CPU MAC. Bits [7:0] is even byte, [15:8] is odd byte. Data sequence specified in Processor Interface application note, ZLAN-26.
Register Table 3 - 3, CPU_FRAME_REG
CMD_STATUS_REG
CPU interface command status This register is not applicable in SSI+MII, MII-only and Remote/No CPU interface modes.
Width 8-bit Default: 00
Access R/W
Address 4
Bit # [0]
Name RXBUF_DONE RXBUF_RDY
Type W R
Description Set Control Frame Receive buffer ready, after CPU writes a complete frame into the buffer. This bit is self-cleared. Control Frame receive buffer ready, CPU can write a new frame 1 - CPU can write a new control command 0 - CPU has to wait until this bit is 1 to write a new control command Set Control Frame Transmit buffer1 ready, after CPU reads out a complete frame from the buffer. This bit is self-cleared. Control Frame transmit buffer1 ready for CPU to read 1 - CPU can read a new control command 1 0 - CPU has to wait until this bit is 1 to read a new control command Set Control Frame Transmit buffer2 ready, after CPU reads out a complete frame from the buffer. This bit is self-cleared. Control Frame transmit buffer2 ready for CPU to read 1 - CPU can read a new control command 1 0 - CPU has to wait until this bit is 1 to read a new control command
[1]
TXBUF1_DONE TXBUF1_RDY
W R
[2]
TXBUF2_DONE TXBUF2_RDY
W R
Register Table 4 - 4, CMD_STATUS_REG
64
Zarlink Semiconductor Inc.
ZL50407
[3] TXFIFO_RXDONE W
Data Sheet
Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and flushed the rest of frame fragment, If occurs. This bit will be self-cleared. Transmit FIFO has data for CPU to read Set this bit to indicate that the following Write to the Receive FIFO is the last one. This bit will be self-cleared. Receive FIFO has space for incoming CPU frame Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. Transmit FIFO End Of Frame Reserved
TXFIFO_RDY [4] RXFIFO_EOF RXFIFO_SPOK [5] RXFIFO_REALIGN
R W R W
TXFIFO_EOF [7:6] RSVD
R R/W
Register Table 4 - 4, CMD_STATUS_REG (continued)
INT_REG
Interrupt sources
Width 8-bit Default: N/A
Access R
Address 5
Bit # [0] [1] [2] [6:3] [7]
Name INT_CPU_FRAME INT_CTL_BUF1 INT_CTL_BUF2 RSVD INT_CHIP_RESET
Type R R R R R
Description Ethernet frame interrupt. Ethernet Frame receive buffer has data for processor to read Control frame 1 interrupt. Control Frame receive buffer 1 has data for processor to read Control frame 2 interrupt. Control Frame receive buffer 2 has data for processor to read Reserved Device Timeout Detected interrupt Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it. Register Table 5 - 5, INT_REG
65
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
CTL_FRAME_BUF1
Used to transmit/receive control frames
Width 16-bit Default: 00
Access R/W
Address 6
Bit # [15:0]
Name CTL_BUF1
Type W
Description Send control frame to command engine. Bits [7:0] is even byte, [15:8] is odd byte. Control frame format specified in Processor Interface application note, ZLAN-26.
R
Receive control frame from command engine. Bits [7:0] is even byte, [15:8] is odd byte. Control frame format specified in Processor Interface application note, ZLAN-26.
Register Table 6 - 6, CTL_FRAME_BUF1
CTL_FRAME_BUF2
Used to receive control frames
Width 16-bit Default: 00
Access R
Address 7
Bit # [15:0]
Name CTL_BUF2
Type R
Description Receive control frame from command engine. Bits [7:0] is even byte, [15:8] is odd byte. Control frame format specified in Processor Interface application note, ZLAN-26.
Register Table 7 - 7, CTL_FRAME_BUF2
12.3 12.3.1
Indirectly Accessed Registers (Group 0 Address) MAC Ports Group ECR1Pn: Port n Control Register
12.3.1.1
IC Address: h000+n; CPU Address: h0000+2n (n = port number) Accessed by CPU and IC (R/W) Port 0 - 7 & 9: (RMAC & GMAC Ports) Bit [0] Flow Control 0 - Enable (Default) 1 - Disable
66
Zarlink Semiconductor Inc.
ZL50407
Bit [1] Duplex Mode 0 - Full Duplex (Default) 1 - Half Duplex - Only in 10/100 mode Speed 0 - 100 Mbps (Default) 1 - 10 Mbps 00 - Enable Auto-Negotiation (Default) This enables hardware state machine for auto-negotiation. 01 - Limited Disable Auto-Negotiation This disables hardware state machine for speed auto-negotiation (use ECR1Pn[2:0] for configuration). Hardware will still poll PHY for link status. 10 - Force Link Down Disable the port. Hardware does not talk to PHY. 11 - Force Link Up The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control) setup. Hardware does not talk to PHY. Asymmetric Flow Control Enable. 0 - Disable asymmetric flow control (Default) 1 - Enable Asymmetric flow control
Data Sheet
Bit [2]
Bits [4:3]
Bit [5]
When this bit is set and flow control is on (bit [0] = 0), the device does not send out flow control frames, but it's receiver interprets and processes flow control frames. Bits [7:6] SS - Spanning tree state (IEEE 802.1D spanning tree protocol) 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
Port 8: (CPU Port) 8/16-bit or Serial Only Modes Bit [5:0] Bits [7:6] Reserved SS - Spanning tree state (IEEE 802.1D spanning tree protocol) 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
Serial + MII Mode Bit [0] Flow Control 0 - Enable (Default) 1 - Disable Duplex Mode Must be 0 - Full Duplex (Default) Speed 0 - 100 Mbps (Default) 1 - 10 Mbps
Bit [1] Bit [2]
67
Zarlink Semiconductor Inc.
ZL50407
Bit [3] 1 - MII Port Up The configuration in ECR1Pn[2:0] is used for (speed/duplex/flow control) setup. 0 - MII Port Down Note: Bit [4] must be `1'. Bit [4] Bit [5] Must be `1'. Asymmetric Flow Control Enable. 0 - Disable asymmetric flow control (Default) 1 - Enable Asymmetric flow control
Data Sheet
When this bit is set and flow control is on (bit [0] = 0), the device does not send out flow control frames, but it's receiver interprets and processes flow control frames. Bits [7:6] SS - Spanning tree state (IEEE 802.1D spanning tree protocol) 00 - Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned. 11 - Forwarding: Frame is forwarded. Source MAC address is learned. (Default)
12.3.1.2
ECR2Pn: Port n Control Register
IC Address: h00A+n; CPU Address: h0001+2n (n = port number) Accessed by CPU and IC (R/W) Bit [0]: Filter untagged frame 0: Disable (Default) 1: All untagged frames from this port are discarded or follow security option when security is enable Filter Tag frame 0: Disable (Default) 1: All tagged frames from this port are discarded or follow security option when security is enable Learning Disable 0: Learning is enabled on this port (Default) 1: Learning is disabled on this port Rate control timer select (RMAC ports only) 0: 10 microsecond refreshing time (Default) 1: 1 millisecond refreshing time 0 Reserved. Must be 0.
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4] Bit [5]
68
Zarlink Semiconductor Inc.
ZL50407
Bits [7:6]
Data Sheet
Security Enable. The ZL50407 checks the incoming data for one of the following conditions: * If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. * A MAC address is defined as secure when its entry at MAC table has static status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted) indicates whether the address is unicast or multicast. As source addresses are always unicast bit 0 is not used (always 0). ZL50407 uses this bit to define secure MAC addresses. * If the port is set as learning disable and the source MAC address of the incoming packet is not defined in the MAC address table or the MAC address is not associated to the ingress port. If any one of the conditions is met, the packet is forwarded based on these setting. 00 - Disable port security, forward packets as usual. (Default) 01 - Discard violating packets 10 - Forward violating packets as usual and also to the CPU for inspection 11 - Forward violating packets to the CPU for inspection It also checks for one of the following additional conditions: * If the port is configured to filter untagged frames and an untagged frame arrives, or * If the port is configured to filter tagged frames and a tagged frame arrives, or * If the packet has the source mac address on the source mac address filter list, or * If the packet has the destination mac address on the destination mac address filter list If any one of the conditions is met, the packet will be handled according to: 0X - Discard violating packets 1X - Forward violating packets to CPU for inspection
12.3.1.3
ECR3Pn: Port n Control Register
IC Address: h014+n; CPU Address: h0080+2n (n = port number) Accessed by CPU and IC (R/W) Bit [0]: Enable receiving short frame < 64B 0: Disable (Default) 1: Allow receiving short frame with correct CRC. Enable receiving long frame > 1522 0: Disable (Default) 1: Allow receiving long frame that are <= BUF_LIMIT value Enable pad frame to 64B when transmitted 0: Allow padding to 64B (Default) 1: Disable Enable compress preamble 0: Send standard preamble (Default) 1: Only one byte preamble+SFD Number of bytes removed from the Inter-Frame Gap (IFG). (Default 0x0)
Bit [1]:
Bit [2]:
Bit [3]:
Bits [6:4]
69
Zarlink Semiconductor Inc.
ZL50407
Bit [7] Link Heart Beat Transmit (RMAC ports only) 0: Disable (Default) 1: Enable
Data Sheet
12.3.1.4
ECR4Pn: Port n Control Register
IC Address: h01E+n; CPU Address: h0081+2n (n = port number) Accessed by CPU and IC (R/W) Port 0 - 7: (RMAC Ports) Bit [1:0]: Enable PHY Mode 00: MAC Mode (Default) 11: PHY Mode (Reverse MII/GPSI) Only valid in MII and GPSI interface modes. In PHY mode, Mn_TXCLK & Mn_RXCLK pins becomes outputs. Bit [2]: Internal loopback. 0: Disable (Default) 1: Enable In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet. Bits [4:3]: Interface mode: 00 - GPSI mode 01 - MII mode 10 - Reserved 11 - RMII mode (Default) Frame loopback. 0: Disable frame from sending back to its source port. (Default) 1: Allow frame to send back to its source port In a regular ethernet switch, a packet should never be receive and forwarded to the same port. Setting the bit allows it to happen. This is not the same as an ingress MAC loopback. The destination MAC address has to be stored (learned) in the MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Link Heart Beat Receive 0: Disable (Default). Also clears all MAC LHB status. 1: Enable Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing.
Bit [5]:
Bit [7]:
70
Zarlink Semiconductor Inc.
ZL50407
Port 8: (CPU Port) Bits [1:0]: Bit [2]: Reserved Enable special write to 2 registers in a single write operation. 0: Disable (Default) 1: Enable Reserved Frame loopback. 0: Disable frame from sending back to its source port. (Default) 1: Allow frame to send back to its source port
Data Sheet
Bit[4:3]: Bit [5]:
In a regular ethernet switch, a packet should never be receive and forwarded to the same port. Setting the bit allows it to happen. This is not the same as an ingress MAC loopback. The destination MAC address has to be stored (learned) in the MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Bit [7]: Reserved Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing.
Port 9: (GMAC Port) Bits [1:0]: Enable PHY Mode 00: MAC Mode (Default) 11: PHY Mode (Reverse MII) Only valid in MII interface mode. In PHY mode, M9_RXCLK pin becomes an output and M9_MTXCLK must be tied to M9_RXCLK externally. Bit [2]: Internal loopback. 0: Disable (Default) 1: Enable In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet. Bits [4:3]: Interface mode: 00 - MII mode 11 - GMII mode (Default) Frame loopback. 0: Disable frame from sending back to its source port. (Default) 1: Allow frame to send back to its source port In a regular ethernet switch, a packet should never be receive and forwarded to the same port. Setting the bit allows it to happen. This is not the same as an ingress MAC loopback. The destination MAC address has to be stored (learned) in the MCT and associated with the originating source port. The frame loopback will only work for unicast packets.
Bit [5]:
71
Zarlink Semiconductor Inc.
ZL50407
Bit [6]: Bit [7]: Reserved Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing.
Data Sheet
12.3.1.5
BUF_LIMIT - Frame Buffer Limit
CPU Address: h0036 Accessed by CPU (R/W) Bits [6:0]: Bit [7]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Reserved
12.3.1.6
FCC - Flow Control Grant Period
CPU Address: h0037 Accessed by CPU (R/W) Bits [2:0]: Flow Control Grant Period. (Default 0x3) Units are (FCC[2:0]+1)*4us Bits [7:3]: Reserved
12.3.2 12.3.2.1
(Group 1 Address) VLAN Group AVTCL - VLAN Type Code Register Low
IC Address: h028; CPU Address: h0100 Accessed by CPU and IC (R/W) Bits [7:0]: VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0x00)
12.3.2.2
AVTCH - VLAN Type Code Register High
IC Address: h029; CPU Address: h0101 Accessed by CPU and IC (R/W) Bits [7:0]: VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
72
Zarlink Semiconductor Inc.
ZL50407
12.3.2.3 PVMAP00_0 - Port 0 Configuration Register 0
Data Sheet
IC Address: h02A, CPU Address: h0102 Accessed by CPU and IC (R/W) Bits [7:0]: VLAN Mask for port 0 (Default 0xFF)
This register indicates the legal egress ports. A "1" on bit 3 means that the packet can be sent to port 3. A "0" on bit 3 means that any packet destined to port 3 will be discarded. This register works with registers 1 to form a 10 bit mask to all egress ports.
12.3.2.4
PVMAP00_1 - Port 0 Configuration Register 1
IC Address: h034, CPU Address: h0103 Accessed by CPU and IC (R/W) Bits [1:0]: Bits [7:2]: VLAN Mask for ports 9 to 8 (Default 0x3) Reserved (Default 0x3F)
12.3.2.5
PVMAP00_3 - Port 0 Configuration Register 3
IC Address: h3E, CPU Address: h0105 Accessed by CPU and IC (R/W) Bits [2:0]: Bits [5:3]: Reserved Default transmit priority. Used when Bit [7]=1 (Default 0) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 ... Transmit Priority Level 6 Transmit Priority Level 7 (Highest) Bit [6]: Default drop precedence. Used when Bit [7]=1 0 - Drop Precedence Level 0 (Lowest) (Default) 1 - Drop Precedence Level 1 (Highest) Enable Fix Priority (Default 0) 0 - Disable. All frames are analysed. Transmit Priority and Drop Precedence are based on VLAN Tag, TOS or Logical Port. 1 - Enable. Transmit Priority and Drop Precedence are based on values programmed in bit [6:3]
Bit [7]:
73
Zarlink Semiconductor Inc.
ZL50407
12.3.2.6 PVMAPnn_0,1,3 - Ports 1~9 Configuration Registers
Data Sheet
PVMAP01_0,1,3 - IC Address h02B, 035, 03F; CPU Address:h0106, 0107, 0109 (Port 1) PVMAP02_0,1,3 - IC Address h02C, 036, 040; CPU Address:h010A, 010B, 010D (Port 2) PVMAP03_0,1,3 - IC Address h02D, 037, 041; CPU Address:h010E, 010F, 0111 (Port 3) PVMAP04_0,1,3 - IC Address h02E, 038, 042; CPU Address:h0112, 0113, 0115 (Port 4) PVMAP05_0,1,3 - IC Address h02F, 039, 043; CPU Address:h0116, 0117, 0119 (Port 5) PVMAP06_0,1,3 - IC Address h030, 03A, 044; CPU Address:h011A, 011B, 011D (Port 6) PVMAP07_0,1,3 - IC Address h031, 03B, 045; CPU Address:h011E, 011F, 0121 (Port 7) PVMAP08_0,1,3 - IC Address h032, 03C, 046; CPU Address:h0122, 0123, 0125 (Port CPU) PVMAP09_0,1,3 - IC Address h033, 03D, 047; CPU Address:h0126, 0127, 0129 (Port GMAC)
12.3.2.7
PVMODE
IC Address: h048, CPU Address: h0170 Accessed by CPU and IC (R/W) Bit [0]: Bit [1]: Reserved. Must be 0. Slow learning (Default = 0) Same function as SE_OPMODE bit [7]. Either bit can enable the function; both need to be turned off to disable the feature. Bit [2]: Disable dropping of frames with destination MAC addresses 01-80-C2-00-00-01 to 0x01-80-C2-00-00-0F. 0: Drop all frames in this range (Default) 1: Disable dropping of frames in this range Flooding control in secure mode 0: Enable - Learning disabled port will not receive any flooding packets (Default) 1: Disable Support MAC address 0 0: MAC address 0 is not learned. (Default) This means packet with destination MAC address 0 is forwarded as unknown destination. It is subjected to unicast to multicast rate control. 1: MAC address 0 is learned. Disable IEEE multicast control frame (01-80-C2-00-00-00 to 01-80-C2-00-00-0F) to CPU in managed mode. In unmanaged mode, frame is forwarded as multicast (except PAUSE frame). 0: Frame is forwarded to CPU (Default) 1: Frame is forwarded as multicast (except PAUSE frame) Reserved. Must be 0. Enable logical port match in secure mode 0: Disable (Default) 1: Enable - When Well Known or User Define logical port force discard enabled, force any IP packet with logical port number matching logical port numbers to CPU.
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]: Bit [7]:
74
Zarlink Semiconductor Inc.
ZL50407
12.3.3 (Group 2 Address) Port Trunking Groups
Data Sheet
Trunk Group - Up to eight RMAC ports can be selected for each trunk group.
12.3.3.1
TRUNKn- Trunk Group 0~7
CPU Address: h0200+n (n = trunk group) Accessed by CPU (R/W) Bit [7:0] Port 7-0 bit map of trunk n. (Default 0) B i t 7 TRUNK0 P o r t 7 P o r t 0 B i t 0
12.3.3.2
TRUNKn_HASH10 - Trunk group n hash result 1/0 destination port number
CPU Address: h0208+4n (n = trunk group) Accessed by CPU (R/W) Bits [3:0] Bits [7:4] Hash result 0 destination port number (Default 0) Hash result 1 destination port number (Default 0)
12.3.3.3
TRUNKn_HASH32 - Trunk group n hash result 3/2 destination port number
CPU Address: h0209+4n (n = trunk group) Accessed by CPU (R/W) Bits [3:0] Bits [7:4] Hash result 2 destination port number (Default 0) Hash result 3 destination port number (Default 0)
75
Zarlink Semiconductor Inc.
ZL50407
12.3.3.4
Data Sheet
TRUNKn_HASH54 - Trunk group n hash result 5/4 destination port number
CPU Address: h020A+4n (n = trunk group) Accessed by CPU (R/W) Bits [3:0] Bits [7:4] Hash result 4 destination port number (Default 0) Hash result 5 destination port number (Default 0)
12.3.3.5
TRUNKn_HASH76 - Trunk group n hash result 7/6 destination port number
CPU Address: h020B+4n (n = trunk group) Accessed by CPU (R/W) Bits [3:0] Bits [7:4] Hash result 6 destination port number (Default 0) Hash result 7 destination port number (Default 0)
Multicast Hash Registers Multicast Hash registers are used to distribute multicast traffic. 16 registers are used to form a 8-entry array; each entry has 10 bits, with each bit representing one port. Any port not belonging to a trunk group should be programmed with 1. Ports belonging to the same trunk group should only have a single port set to "1" per entry. The port set to "1" is picked to transmit the multicast frame when the hash value is met. Hash Value =0 Hash Value =1 Hash Value =2 Hash Value =3 Hash Value =4 Hash Value =5 Hash Value =6 Hash Value =7 HASH0-1 HASH1-1 HASH2-1 HASH3-1 HASH4-1 HASH5-1 HASH6-1 HASH7-1 P o r t 9 P o r t 8 HASH0-0 HASH1-0 HASH2-0 HASH3-0 HASH4-0 HASH5-0 HASH6-0 HASH7-0 P o r t 7 P o r t 0
76
Zarlink Semiconductor Inc.
ZL50407
12.3.3.6 MULTICAST_HASHn-0 - Multicast hash result 0~7 mask byte 0
Data Sheet
CPU Address: h0228+2n (n = hash value) Accessed by CPU (R/W) Bits [7:0]: Port 7-0 bit map for multicast hash. (Default 0xFF)
12.3.3.7
MULTICAST_HASHn-1 - Multicast hash result 0~7 mask byte 1
CPU Address: h0229+2n (n = hash value) Accessed by CPU (R/W) Bits [1:0]: Bit [2]: Bits [5:3]: Bits [7:6]: Port 9-8 bit map for multicast hash. (Default 0x3) Reserved (Default 0x1) Reserved (Default 0x7) MULTICAST_HASH0-1 Hash Select. The hash algorithm selected is valid for all trunks 00 - Use Source and Destination MAC Address for hashing 01 - Use Source MAC Address for hashing 10 - Use Destination MAC Address for hashing 11 - Use Source Port Number for hashing (Default) MULTICAST_HASH[7:1]-1 Reserved (Default 0x3)
12.3.4
(Group 3 Address) CPU Port Configuration Group
47 MAC5 MAC4 MAC3 MAC2 MAC1 MAC0 0 (MC bit)
MAC5 to MAC0 registers form the CPU MAC address. When a packet with destination MAC address match MAC [5:0], the packet is forwarded to the CPU. The default MAC address is 00-00-00-00-00-00.
12.3.4.1
MAC0 - CPU MAC address byte 0
CPU Address: h0300 Accessed by CPU (R/W) Bits [7:0]: Byte 0 (bits [7:0]) of the CPU MAC address (Default 0)
77
Zarlink Semiconductor Inc.
ZL50407
12.3.4.2 MAC1 - CPU MAC address byte 1
Data Sheet
CPU Address: h0301 Accessed by CPU (R/W) Bits [7:0]: Byte 1 (bits [15:8]) of the CPU MAC address (Default 0)
12.3.4.3
MAC2 - CPU MAC address byte 2
CPU Address: h0302 Accessed by CPU (R/W) Bits [7:0]: Byte 2 (bits [23:16]) of the CPU MAC address (Default 0)
12.3.4.4
MAC3 - CPU MAC address byte 3
CPU Address: h0303 Accessed by CPU (R/W) Bits [7:0]: Byte 3 (bits [31:24]) of the CPU MAC address (Default 0)
12.3.4.5
MAC4 - CPU MAC address byte 4
CPU Address: h0304 Accessed by CPU (R/W) Bits [7:0]: Byte 4 (bits [39:32]) of the CPU MAC address (Default 0)
12.3.4.6
MAC5 - CPU MAC address byte 5
CPU Address: h0305 Accessed by CPU (R/W) Bits [7:0]: Byte 5 (bits [47:40]) of the CPU MAC address (Default 0) Note: Bits [42:40] are set on a per port basis using MAC01, MAC23, MAC45, MAC67 registers. For port 9, this register is ignored and MAC9 is used for bits [47:40].
12.3.4.7
INT_MASK0 - Interrupt Mask
CPU Address: h0306 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn't want to be interrupted. (Default 0x00) 1: Mask the interrupt 0: Unmask the interrupt (Enable interrupt) (Default)
78
Zarlink Semiconductor Inc.
ZL50407
Bit [0]: Bit [1]: Bit [2]: Bits [6:3]: Bit [7]: CPU frame interrupt. CPU frame buffer has data for CPU to read
Data Sheet
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read Reserved Device Timeout Detected interrupt
12.3.4.8
INTP_MASK0 - Interrupt Mask for MAC Port 0,1
CPU Address: h0310 Accessed by CPU (R/W) The CPU can dynamically mask the interrupt when it is busy and doesn't want to be interrupted (Default 0x00) 1: Mask the interrupt 0: Unmask the interrupt (Default) Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic counter wraps around. Refer to hardware statistic counter for interrupt sources Port 0 link change mask Port 0 module detect mask Reserved Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic counter wraps around. Refer to hardware statistic counter for interrupt sources. Port 1 link change mask Port 1 module detect mask Reserved
Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]
12.3.4.9
INTP_MASKn - Interrupt Mask for MAC Ports 2~9 Registers
INTP_MASK1 - CPU Address: h0311 (Ports 2,3) INTP_MASK2 - CPU Address: h0312 (Ports 4,5) INTP_MASK3 - CPU Address: h0313 (Ports 6,7) INTP_MASK4 - CPU Address: h0314 (Port CPU,GMAC)
79
Zarlink Semiconductor Inc.
ZL50407
12.3.4.10 RQS - Receive Queue Select
Data Sheet
CPU Address: h0323 Accessed by CPU (RW) Select which receive queue is being used by the CPU port. Bit [0]: Select Queue 0 0: Not selected (Default) 1: Selected Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Select Queue 1 Select Queue 2 Select Queue 3 Select Multicast Queue 0 Select Multicast Queue 1 Select Multicast Queue 2 Select Multicast Queue 3
Note: Strict priority applies between different selected queues (UQ3>UQ2>UQ1>UQ0>MQ3>MQ2>MQ1>MQ0).
12.3.4.11
RQSS - Receive Queue Status
CPU Address: h0324 Accessed by CPU (RO) CPU receive queue status Bits [3:0]: Unicast Queue 3 to 0 not empty 0: Empty 1: Not Empty Bits [7:4]: Multicast Queue 3 to 0 not empty
12.3.4.12
MAC01 - Increment MAC port 0,1 address
CPU Address: h0325 Accessed by CPU (RW) Bits [2:0]: Bit [3]: Bits [6:4]: Bit [7]: Bits [42:40] of Port 0 CPU MAC address Reserved Bits [42:40] of Port 1 CPU MAC address Reserved
MAC01, MAC23, MAC45, MAC67, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC address on a per port basis.
80
Zarlink Semiconductor Inc.
ZL50407
12.3.4.13 MAC23 - Increment MAC port 2,3 address
Data Sheet
CPU Address: h0326 Accessed by CPU (RW) Bits [2:0]: Bit [3]: Bits [6:4]: Bit [7]: Bits [42:40] of Port 2 CPU MAC address Reserved Bits [42:40] of Port 3 CPU MAC address Reserved
12.3.4.14
MAC45 - Increment MAC port 4,5 address
CPU Address: h0327 Accessed by CPU (RW) Bits [2:0]: Bit [3]: Bits [6:4]: Bit [7]: Bits [42:40] of Port 4 CPU MAC address Reserved Bits [42:40] of Port 5 CPU MAC address Reserved
12.3.4.15
MAC67 - Increment MAC port 6,7 address
CPU Address: h0328 Accessed by CPU (RW) Bits [2:0]: Bit [3]: Bits [6:4]: Bit [7]: Bits [42:40] of Port 6 CPU MAC address Reserved Bits [42:40] of Port 7 CPU MAC address Reserved
12.3.4.16
MAC9 - Increment MAC port 9 address
CPU Address: h0329 Accessed by CPU (RW) Bits [7:0]: Bits [47:40] of Port 9 CPU MAC address
81
Zarlink Semiconductor Inc.
ZL50407
12.3.4.17 CPUQINS0 - CPUQINS6 - CPU Queue Insertion Command
Data Sheet
CPU Address: h0330-0336 Accessed by CPU, (R/W) 55 CQ6 CQ5 CQ4 CQ3 CQ2 CQ1 CQ0 0
CPU Queue insertion command CPUQINS0 Bit[7:0]: CPUQINS1 Bit[9:8]: Bits [13:10] Bits [15:14] CPUQINS2 Bits [20:16] Bits [23:21] CPUQINS3 Bits [31:24] CPUQINS4 Bits [35:32] Bits [39:36] CPUQINS5 Bits [47:40] CPUQINS6 Bits [50:48] Bit [51] Bits [54:52] Bit [55] Header Pointer (con't) Multicast frame (has to be one if more than one destination port) Reserved Command valid (will be processed on the rising edge of the signal) Header Pointer (con't) Tail pointer (con't) Header Pointer Tail pointer (con't) Number of granules for the frame (con't) Tail pointer Destination Map (GMAC, CPU). Priority Number of granules for the frame Destination Map (port 7-0).
82
Zarlink Semiconductor Inc.
ZL50407
12.3.4.18 CPUQINSRPT - CPU Queue Insertion Report
Data Sheet
CPU Address: h0337 Accessed by CPU, (RO) CPU command queue status Bit [0]: Bit [1]: The command is under processing. Insertion Fail (May be due to queue full, WRED or filtering)
12.3.4.19
CPUGRNHDL0 - CPUGRNHDL1 - CPU Allocated Granule Pointer
CPU Address: h0338-339 Accessed by CPU, (RO) 15 CG1 CPU Queue insertion command Bits [14:0]: Bit [15]: Granule pointer. Pointer valid CG0 0
12.3.4.20
CPURLSINFO0 - CPURLSINFO4 - Receive Queue Status
CPU Address: h033A-033E Accessed by CPU, (R/W) 0 CR4 CPU Queue insertion command Bits [14:0]: Bits [30:15] Bits [38:32] Header pointer Tail pointer Number of granules for the release CR3 CR2 CR1 CR0
83
Zarlink Semiconductor Inc.
ZL50407
12.3.4.21 CPUGRNCTR - CPU Granule Control
Data Sheet
CPU Address: h033f Accessed by CPU, (R/W) CPU receive queue status Bit [0]: Bit [1]: Bit [2]: Allocate granule to the CPU if set to one. Otherwise, do not allocate any resource. Read allocated granule (at rising edge only) Release info valid (will be processed at rising edge only)
12.3.5 12.3.5.1
(Group 4 Address) Search Engine Group AGETIME_LOW - MAC address aging time Low
IC Address: h049; CPU Address: h0400 Accessed by CPU and IC (R/W) Used in conjuction with AGETIME_HIGH. The ZL50407 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bits [7:0]: Low byte of the MAC address aging timer (Default 0x5C)
12.3.5.2
AGETIME_HIGH -MAC address aging time High
IC Address: h04A; CPU Address: h0401 Accessed by CPU and IC (R/W) Bits [7:0]: High byte of the MAC address aging timer (Default 0x00)
The default setting of AGETIME_LOW/HIGH provides 300 seconds aging time. Aging time is based on the following equation: {AGETIME_HIGH,AGETIME_LOW} X (# of MAC entries in the memory X 800 sec). Number of MAC entries = 4 K.
12.3.5.3
SE_OPMODE - Search Engine Operation Mode
CPU Address: h0403 Accessed by CPU (R/W) Note: ECR2[2] enable/disable learning for each port. Bit [0]: Bit [1]: Reserved. Must be 0. Protocol filtering mode 0 - Inclusive (Default) 1 - Exclusive
84
Zarlink Semiconductor Inc.
ZL50407
Bit [2]:
Data Sheet
Delete MAC report control 0 - Report MAC address deletion (MAC address is deleted from MCT after aging time) (Default) 1 - Disable report MAC address deletion Delete Control 0 - MAC address entry is removed when it is old enough to be aged (Default) 1 - Disable aging logic from removing MAC during aging However, a report is still sent to the CPU in both cases, when bit [2] = 0
Bit [3]:
Bit [4]: Bit [5] Bit [6]:
Reserved. Must be 0. Reserved Disable MCT speed-up aging 0 - Enable speed-up aging when MCT resource is low. (Default) 1 - Disable speed-up aging when MCT resource is low. Slow Learning 0 - Learning is performed independent of search demand (Default) 1 - Enable slow learning. Learning is temporary disabled when search demand is high
Bit [7]:
12.3.6 12.3.6.1
(Group 5 Address) Buffer Control/QOS Group QOSC - QOS Control
IC Address: h04B; CPU Address: h0500 Accessed by CPU and I2C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 0 - Disable (Default) 1 - Enable Enable RX rate control (on RMAC ports only) 0 - Disable (Default) 1 - Enable Reserved Select VLAN tag or TOS (IP packets) to be preferentially picked to map transmit priority and drop precedence 0 - Select VLAN Tag priority field over TOS (Default) 1 - Select TOS over VLAN tag priority field Select TOS bits for transmission priority 0 - Use TOS [4:2] bits to map the transmit priority (Default) 1 - Use TOS [7:5] bits to map the transmit priority Select TOS bits for drop precedence 0 - Use TOS [4:2] bits to map the drop precedence (Default) 1 - Use TOS [7:5] bits to map the drop precedence
Bit [1]:
Bits [4:2]: Bit [5]:
Bit [6]:
Bit [7]:
85
Zarlink Semiconductor Inc.
ZL50407
12.3.6.2
2
Data Sheet
PCC - Packet Congestion Control
I C Address: h068; CPU Address: h0510 Accessed by CPU and I2C (R/W) Bits [7:0]: Packet congestion control on the granule count of P0 queue. Used to trigger RED at B% when destination port's P0 queue granule count reaches PCC and shared pool is all in use. Granularity is 16 granule (Default 0x6). See Programming QoS Registers application note, ZLAN-42, for more information
12.3.6.3
MCC - Multicast Congestion Control
IC Address: h069; CPU Address: h0511 Accessed by CPU and IC (R/W) Bits [7:0]: Global congestion control on the multicast granule count. Used to trigger 100% drop (or flow control, if FC enabled on source port) when total multicast granule count reaches MCC. Granularity is 16 granule (Default 0x6). See Programming QoS Registers application note, ZLAN-42, for more information
12.3.6.4
MCCTH - Multicast Threshold Control
CPU Address: h0512 Accessed by CPU (R/W) Bits [7:0]: Global congestion control threshold on the multicast granule count. Exceeding the MCCTH threshold is considered as an indication of multicast resources being low. Used to trigger RED at B% when when total multicast granule count reaches MCCTH. Granularity is 16 granule (Default 0x3). See Programming QoS Registers application note, ZLAN-42, for more information
12.3.6.5
RDRC0 - WRED Rate Control 0
IC Address: h090; CPU Address: h0513 Accessed by CPU and I2C (R/W) Bits [3:0]: Corresponds to the frame drop percentage Y% for WRED. Granularity 6.25%. Corresponds to the frame drop percentage X% for WRED. Granularity 6.25%.
Bits [7:4]:
See Programming QoS Registers application note, ZLAN-42, for more information
86
Zarlink Semiconductor Inc.
ZL50407
12.3.6.6 RDRC1 - WRED Rate Control 1
Data Sheet
IC Address: h091; CPU Address: h0514 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Corresponds to the frame drop percentage B% for RED. Granularity 6.25%. Corresponds to the frame drop percentage Z% for WRED. Granularity 6.25%.
See Programming QoS Registers application note, ZLAN-42, for more information
12.3.6.7
RDRC2 - WRED Rate Control 2
CPU Address: h0515 Accessed by CPU (R/W) Bits [3:0]: Corresponds to the frame drop percentage RB% for ingress rate control. Granularity 6.25%. Corresponds to the frame drop percentage RA% for ingress rate control. Granularity 6.25%.
Bits [7:4]:
See Rate Control application note, ZLAN-33, for more information
12.3.6.8
SFCB - Share FCB Size
IC Address: h074; CPU Address: h0518 Accessed by CPU and IC (R/W) Bits [7:0]: Expressed in multiples of 16 granules. Buffer reservation for shared pool.
12.3.6.9
C1RS - Class 1 Reserve Size
IC Address: h075; CPU Address: h0519 Accessed by CPU and IC (R/W) Bits [7:0]: Class 1 FCB Reservation
Buffer reservation for class 1. Granularity 16 granules. (Default 0)
12.3.6.10
C2RS - Class 2 Reserve Size
IC Address: h076; CPU Address: h051A Accessed by CPU and IC (R/W) Bits [7:0]: Class 2 FCB Reservation
Buffer reservation for class 2. Granularity 16 granules. (Default 0)
87
Zarlink Semiconductor Inc.
ZL50407
12.3.6.11 C3RS - Class 3 Reserve Size
Data Sheet
IC Address: h077; CPU Address: h051B Accessed by CPU and IC (R/W) Bits [7:0]: Class 3 FCB Reservation
Buffer reservation for class 3. Granularity 16 granules. (Default 0)
12.3.6.12
AVPML - VLAN Tag Priority Map
IC Address: h056; CPU Address: h0530 Accessed by CPU and IC (R/W) Registers AVPML, AVPMM, and AVPMH allow the eight VLAN Tag priorities to map into eight Internal level transmit priorities. Under the Internal transmit priority, seven is the highest priority where as zero is the lowest. This feature allows the user the flexibility of redefining the VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50407. When the packet goes out it carries the original priority. Bits [2:0]: Priority when the VLAN tag priority field is 0 (Default 0) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 ... Transmit Priority Level 6 Transmit Priority Level 7 (Highest) Bits [5:3]: Bits [7:6]: Priority when the VLAN tag priority field is 1 (Default 0) Priority when the VLAN tag priority field is 2 (Default 0)
12.3.6.13
AVPMM - VLAN Priority Map
IC Address: h057; CPU Address: h0531 Accessed by CPU and IC (R/W) Map VLAN priority into eight level transmit priorities: Bit [0]: Bits [3:1]: Bits [6:4]: Bit [7]: Priority when the VLAN tag priority field is 2 (Default 0) Priority when the VLAN tag priority field is 3 (Default 0) Priority when the VLAN tag priority field is 4 (Default 0) Priority when the VLAN tag priority field is 5 (Default 0)
88
Zarlink Semiconductor Inc.
ZL50407
12.3.6.14 AVPMH - VLAN Priority Map
Data Sheet
IC Address: h058; CPU Address: h0532 Accessed by CPU and IC (R/W) Map VLAN priority into eight level transmit priorities: Bits [1:0]: Bits [4:2]: Bits [7:5]: Priority when the VLAN tag priority field is 5 (Default 0) Priority when the VLAN tag priority field is 6 (Default 0) Priority when the VLAN tag priority field is 7 (Default 0)
12.3.6.15
AVDM - VLAN Discard Map
IC Address: h05C; CPU Address: h0533 Accessed by CPU and IC (R/W) Map VLAN priority into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop precedence when VLAN Tag priority field is 0 (Default 0) 0 - Drop Precedence Level 0 (Lowest) (Default) 1 - Drop Precedence Level 1 (Highest) Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Frame drop precedence when VLAN Tag priority field is 1 (Default 0) Frame drop precedence when VLAN Tag priority field is 2 (Default 0) Frame drop precedence when VLAN Tag priority field is 3 (Default 0) Frame drop precedence when VLAN Tag priority field is 4 (Default 0) Frame drop precedence when VLAN Tag priority field is 5 (Default 0) Frame drop precedence when VLAN Tag priority field is 6 (Default 0) Frame drop precedence when VLAN Tag priority field is 7 (Default 0)
12.3.6.16
TOSPML - TOS Priority Map
IC Address: h059; CPU Address: h0540 Accessed by CPU and IC (R/W) Map TOS field in IP packet into eight level transmit priorities Bits [2:0]: Priority when the TOS field is 0 (Default 0) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 ... Transmit Priority Level 6 Transmit Priority Level 7 (Highest)
89
Zarlink Semiconductor Inc.
ZL50407
Bits [5:3]: Bits [7:6]: Priority when the TOS field is 1 (Default 0) Priority when the TOS field is 2 (Default 0)
Data Sheet
12.3.6.17
TOSPMM - TOS Priority Map
IC Address: h05A; CPU Address: h0541 Accessed by CPU and IC (R/W) Map TOS field in IP packet into eight level transmit priorities Bit [0]: Bits [3:1]: Bits [6:4]: Bit [7]: Priority when the TOS field is 2 (Default 0) Priority when the TOS field is 3 (Default 0) Priority when the TOS field is 4 (Default 0) Priority when the TOS field is 5 (Default 0)
12.3.6.18
TOSPMH - TOS Priority Map
IC Address: h05B; CPU Address: h0542 Accessed by CPU and IC (R/W) Map TOS field in IP packet into eight level transmit priorities: Bits [1:0]: Bits [4:2]: Bits [7:5]: Priority when the TOS field is 5 (Default 0) Priority when the TOS field is 6 (Default 0) Priority when the TOS field is 7 (Default 0)
12.3.6.19
TOSDML - TOS Discard Map
IC Address: h05D; CPU Address: h0543 Accessed by CPU and IC (R/W) Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop precedence when TOS field is 0 (Default 0) 0 - Drop Precedence Level 0 (Lowest) (Default) 1 - Drop Precedence Level 1 (Highest) Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Frame drop precedence when TOS field is 1 (Default 0) Frame drop precedence when TOS field is 2 (Default 0) Frame drop precedence when TOS field is 3 (Default 0) Frame drop precedence when TOS field is 4 (Default 0) Frame drop precedence when TOS field is 5 (Default 0)
90
Zarlink Semiconductor Inc.
ZL50407
Bit [6]: Bit [7]: Frame drop precedence when TOS field is 6 (Default 0) Frame drop precedence when TOS field is 7 (Default 0)
Data Sheet
12.3.6.20
USER_PROTOCOL_n - User Define Protocol 0~7
IC Address: h0B3+n; CPU Address: h0550+n Accessed by CPU and IC (R/W) (Default 00) This register is duplicated eight times from PROTOCOL 0~7 and allows the CPU to define eight separate protocols. Bits [7:0]: User Define Protocol
12.3.6.21
USER_PROTOCOL_FORCE_DISCARD - User Define Protocol 0~7 Force Discard
IC Address: h0BB; CPU Address: h0558 Accessed by CPU and IC (R/W) Bit [0]: Enable Protocol 0 Force Discard 1 - Enable 0 - Disable Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Enable Protocol 1 Force Discard Enable Protocol 2 Force Discard Enable Protocol 3 Force Discard Enable Protocol 4 Force Discard Enable Protocol 5 Force Discard Enable Protocol 6 Force Discard Enable Protocol 7 Force Discard
User Defined Logical Ports and Well Known Ports The ZL50407 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: * * * * * * * * 23 512 6000 443 111 22555 22 554
91
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
register.
Their respective priority can be programmed via WELL_KNOWN_PORT[7:0]_PRIORITY WELL_KNOWN_PORT[_ENABLE can individually turn on/off each Well Known Port if desired.
Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7 registers. Two registers are required to be programmed for the logical port number. The respective priority can be programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via User_Port_Enable register. The User Defined Range provides a range of logical port numbers with the same priority level. Programming is similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in RPRIORITY.
12.3.6.22
WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority
IC Address: h0A8; CPU Address: h0560 Accessed by CPU and IC (R/W) Bits [3:0]: Priority setting, transmission + dropping, for Well known port 0 (23 for telnet) Bit[0] 0 - Drop Precedence Level 0 (Lowest) (Default) 1 - Drop Precedence Level 1 (Highest)
Bits[3:1] Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 ... Transmit Priority Level 6 Transmit Priority Level 7 (Highest) Bits [7:4]: Priority setting, transmission + dropping, for Well known port 1 (512 for TCP/UDP)
12.3.6.23
WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority
IC Address: h0A9; CPU Address: h0561 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Priority setting, transmission + dropping, for Well known port 2 (6000 for XWIN) Priority setting, transmission + dropping, for Well known port 3 (443 for HTTP sec)
92
Zarlink Semiconductor Inc.
ZL50407
12.3.6.24
Data Sheet
WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority
IC Address h0AA, CPU Address 562 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Priority setting, transmission + dropping, for Well known port 4 (111 for sun remote procedure call) Priority setting, transmission + dropping, for Well known port 5 (22555 for IP Phone call setup)
12.3.6.25
WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority
IC Address: h0AB; CPU Address: h0563 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Priority setting, transmission + dropping, for Well known port 6 (22 for ssh) Priority setting, transmission + dropping, for Well known port 7 (554 for rtsp)
12.3.6.26
WELL_KNOWN_PORT_ENABLE - Well Known Logic Port 0 to 7 Enables
IC Address: h0AC; CPU Address: h0564 Accessed by CPU and IC (R/W) Bit [0]: Enable Well Known Port 0 Priority 1 - Enable 0 - Disable Enable Well Known Port 1 Priority Enable Well Known Port 2 Priority Enable Well Known Port 3 Priority Enable Well Known Port 4 Priority Enable Well Known Port 5 Priority Enable Well Known Port 6 Priority Enable Well Known Port 7 Priority
Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]:
12.3.6.27 Discard
WELL_KNOWN_PORT_FORCE_DISCARD - Well Known Logic Port 0~7 Force
IC Address: h0AD; CPU Address: h0565 Accessed by CPU and IC (R/W) Bit [0]: Enable Well Known Port 0 Force Discard 1 - Enable 0 - Disable
93
Zarlink Semiconductor Inc.
ZL50407
Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Enable Well Known Port 1 Force Discard Enable Well Known Port 2 Force Discard Enable Well Known Port 3 Force Discard Enable Well Known Port 4 Force Discard Enable Well Known Port 5 Force Discard Enable Well Known Port 6 Force Discard Enable Well Known Port 7 Force Discard
Data Sheet
12.3.6.28
USER_PORT[7:0]_[LOW/HIGH] - User Define Logical Port 0~7
IC Address: h092+n(Low); CPU Address: h0570+2n(Low) (n = logical port number) IC Address: h09A+n(High); CPU Address: h0571+2n(High) Accessed by CPU and IC (R/W) (Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define eight separate ports. 7 TCP/UDP Logic Port Low 7 TCP/UDP Logic Port High 0 0
12.3.6.29
USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
IC Address: h0A2; CPU Address: h0590 Accessed by CPU and IC (R/W) The chip allows the CPU to define the priority Bits [3:0]: Priority setting, transmission + dropping, for logic port 0 Bit[0] 0 - Drop Precedence Level 0 (Lowest) (Default) 1 - Drop Precedence Level 1 (Highest)
Bits[3:1] Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 ... Transmit Priority Level 6 Transmit Priority Level 7 (Highest) Bits [7:4]: Priority setting, transmission + dropping, for logic port 1 (Default 00)
94
Zarlink Semiconductor Inc.
ZL50407
12.3.6.30 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority
Data Sheet
IC Address: h0A3; CPU Address: h0591 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Priority setting, transmission + dropping, for logic port 2 Priority setting, transmission + dropping, for logic port 3 (Default 00)
12.3.6.31
USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority
IC Address: h0A4; CPU Address: h0592 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Priority setting, transmission + dropping, for logic port 4 Priority setting, transmission + dropping, for logic port 5 (Default 00)
12.3.6.32
USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority
IC Address: h0A5; CPU Address: h0593 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Priority setting, transmission + dropping, for logic port 6 Priority setting, transmission + dropping, for logic port 7 (Default 00)
12.3.6.33
USER_PORT_ENABLE[7:0] - User Define Logic Port 0 to 7 Enables
IC Address: h0A6; CPU Address: h0594 Accessed by CPU and IC (R/W) Bit [0]: Enable User Port 0 Priority 1 - Enable 0 - Disable Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Enable User Port 1 Priority Enable User Port 2 Priority Enable User Port 3 Priority Enable User Port 4 Priority Enable User Port 5 Priority Enable User Port 6 Priority Enable User Port 7 Priority
95
Zarlink Semiconductor Inc.
ZL50407
12.3.6.34
Data Sheet
USER_PORT_FORCE_DISCARD[7:0] - User Define Logic Port 0~7 Force Discard
IC Address: h0A7; CPU Address: h0595 Accessed by CPU and IC (R/W) Bit [0]: Enable User Port 0 Force Discard 1 - Enable 0 - Disable Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Enable User Port 1 Force Discard Enable User Port 2 Force Discard Enable User Port 3 Force Discard Enable User Port 4 Force Discard Enable User Port 5 Force Discard Enable User Port 6 Force Discard Enable User Port 7 Force Discard
12.3.6.35
RLOWL - User Define Range Low Bit 7:0
IC Address: h0AE; CPU Address: h05A0 Accessed by CPU and IC (R/W) Bits [7:0]: Lower 8 bit of the User Define Logical Port Low Range
12.3.6.36
RLOWH - User Define Range Low Bit 15:8
IC Address: h0AF; CPU Address: h05A1 Accessed by CPU and IC (R/W) Bits [7:0]: Upper 8 bit of the User Define Logical Port Low Range
12.3.6.37
RHIGHL - User Define Range High Bit 7:0
IC Address: h0B0; CPU Address: h05A2 Accessed by CPU and IC (R/W) Bits [7:0]: Lower 8 bit of the User Define Logical Port High Range
96
Zarlink Semiconductor Inc.
ZL50407
12.3.6.38 RHIGHH - User Define Range High Bit 15:8
Data Sheet
IC Address: h0B1; CPU Address: h05A3 Accessed by CPU and IC (R/W) Bits [7:0]: Upper 8 bit of the User Define Logical Port High Range
12.3.6.39
RPRIORITY - User Define Range Priority
IC Address: h0B2; CPU Address: h05A4 Accessed by CPU and IC (R/W) RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bit [0]: Drop Precedence (inclusive only) 0 - Drop Precedence Level 0 (Lowest) (Default) 1 - Drop Precedence Level 1 (Highest) Bits [3:1] Transmit Priority (inclusive only) Transmit Priority Level 0 (Lowest) Transmit Priority Level 1 ... Transmit Priority Level 6 Transmit Priority Level 7 (Highest) Bits [5:4] Bits [7:6] Reserved 00 - No Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH) 10 - Inclusive Filtering (RLOW12.3.7 12.3.7.1
(Group 6 Address) MISC Group MII_OP0 - MII Register Option 0
IC Address: h0BC; CPU Address: h0600 Accessed by CPU and IC (R/W) Bits [4:0]: Vendor specified link status register address (null value means don't use it) (Default 00). This is used if the Linkup bit position in the PHY is non-standard Disable jabber detection. This is for HomePNA applications or any serial operation slower than 10 Mbps. 0 = Enable 1 = Disable Reserved
Bits [5]
Bits [6]
97
Zarlink Semiconductor Inc.
ZL50407
Bit [7]: Half duplex flow control feature 0 = Half duplex flow control always enable 1 = Half duplex flow control by negotiation
Data Sheet
12.3.7.2
MII_OP1 - MII Register Option 1
IC Address: h0BD; CPU Address: h0601 Accessed by CPU and IC (R/W) Bits [3:0]: Bits [7:4]: Duplex bit location in vendor specified register Speed bit location in vendor specified register (Default 00)
12.3.7.3
FEN - Feature Enable Register
IC Address: h0BE; CPU Address: h0602 Accessed by CPU and IC (R/W) Bit [0]: Statistic Counter 0 - Disable (Default) 1 - Enable (all ports) When statistic counter is enable, an interrupt control frame is generated to the CPU, every time a counter wraps around. This feature requires an external CPU. Bit [1]: Bit [2]: 0 Support DS EF Code. 0 - Disable (Default) 1 - Enable (all ports) When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0. Bit [3]: Bit [4]: Bit [5]: Reserved. Must be 0. Reserved. Must be 1. Report to CPU 0 - Disable (Default) 1 - Enable When disable new MAC address report or aging reports are disable for all ports. When enable, register SE_OPMODE is used to enable/disable selectively each function. Bit [6]: MII Management State Machine 0: Enable (Default) 1: Disable This bit must be set so that there is no contention on the MDIO bus between MII Management state machine and MIIC & MIID PHY register accesses.
98
Zarlink Semiconductor Inc.
ZL50407
Bit [7]: MCT Link List structure 0 - Enable (Default) 1 - Disable
Data Sheet
12.3.7.4
MIIC0 - MII Command Register 0
CPU Address: h0603 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [7:0]
Note: Before programming MII command: set FEN[6]; check MIIC3, making sure RDY; then program MII command.
12.3.7.5
MIIC1 - MII Command Register 1
CPU Address: h0604 Accessed by CPU (R/W) Bits [7:0]: MII Command Data [15:8]
12.3.7.6
MIIC2 - MII Command Register 2
CPU Address: h0605 Accessed by CPU (R/W) Bits [4:0] Bits [6:5] REG_AD - Register PHY Address OP - Operation code "10" for read command "01" for write command Reserved
Bits [7]
12.3.7.7
MIIC3 - MII Command Register 3
CPU Address: h0606 Accessed by CPU (R/W) Bits [4:0] Bit [5] Bit [6] Bit [7] PHY_AD - 5-bit PHY address Reserved VALID - Data valid from PHY (Read Only) RDY - MII management interface ready (Read Only)
Note: Writing to this register will initiate a serial management cycle to the MII management interface.
99
Zarlink Semiconductor Inc.
ZL50407
12.3.7.8 MIID0 - MII Data Register 0
Data Sheet
CPU Address: h0607 Accessed by CPU (RO) Bits [7:0]: MII Data [7:0]
12.3.7.9
MIID1 - MII Data Register 1
CPU Address: h0608 Accessed by CPU (RO) Bits [7:0]: MII Data [15:8]
12.3.7.10
USD - One Micro Second Divider
CPU Address: h0609 Accessed by CPU (R/W) Bits [5:0]: Divider to get one micro second from M_CLK (only used when not in standard RMII mode) In a MII or GPSI system, a 50 MHz M_CLK may not be available. The system designer can decide to use another frequency on the M_CLK signal. To compensate for this, this register is required to be programmed. For example. If 20 MHz is used on M_CLK, to compensate for the difference, this register is programmed with 20 to provide 1 usec for internal reference. Bits [7:6]: Reserved
12.3.7.11
DEVICE - Device Mode
CPU Address: h060A Accessed by CPU (R/W) Bit [0]: Bit [1]: Reserved CPU Interrupt Polarity 0: Negative Polarity 1: Positive Polarity (Default) Reserved Device ID (Default 0x0). See application note ZLAN-26, Processor Interface, for usage.
Bits [4:2]: Bits [7:5]:
100
Zarlink Semiconductor Inc.
ZL50407
12.3.7.12 CHECKSUM - EEPROM Checksum
Data Sheet
IC Address: 0FF; CPU Address: h060B Accessed by CPU and IC (R/W) Bits [7:0]: Checksum content (Default 0)
This register is used in unmanaged mode only. Before requesting that the ZL50407 updates the EEPROM device, the correct checksum needs to be calculated and written into this checksum register. The checksum formula is:
FF
i=0
IC register = 0
When the ZL50407 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50407 does not start and pin CHECKSUM_OK is set to zero.
12.3.7.13
LHBTimer - Link Heart Beat Timeout Timer
CPU Address: h0610 Accessed by CPU (R/W) In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in this period.
12.3.7.14
LHBReg0, LHBReg1 - Link Heart Beat OpCode
CPU Address: h0611, h6012 Accessed by CPU (R/W) The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the operation code (we recommend h00-12).
12.3.7.15
fMACCReg0, fMACCReg1 - MAC Control Frame OpCode
CPU Address: h0613, h0614 Accessed by CPU (R/W) The registers define the operation code if MAC control frame is forced out by processor.
12.3.7.16
FCB Base Address Register 0
IC Address: h0BF; CPU Address: h0620 Accessed by CPU and IC (R/W) Bits [7:0] FCB Base address bit 7:0 (Default 0)
101
Zarlink Semiconductor Inc.
ZL50407
12.3.7.17 FCB Base Address Register 1
Data Sheet
IC Address: h0C0; CPU Address: h0621 Accessed by CPU and IC (R/W) Bits [7:0] FCB Base address bit 15:8 (Default 0x60)
12.3.7.18
FCB Base Address Register 2
IC Address: h0C1; CPU Address: h0622 Accessed by CPU and IC (R/W) Bits [7:0] FCB Base address bit 23:16 (Default 0)
12.3.8 12.3.8.1
(Group 7 Address) Port Mirroring Group MIRROR CONTROL - Port Mirror Control Register
CPU Address: h070C Accessed by CPU (R/W) (Default 00) Bits [3:0]: Bit [4] Bit [5] Bit [6]: Bit [7]: Destination port to be mirrored to. Mirror Flow from MIRROR_SRC_MAC[5:0] to MIRROR_DEST_MAC[5:0] Mirror Flow from MIRROR_DEST_MAC[5:0] to MIRROR_SRC_MAC[5:0] Mirror when address is destination Mirror when address is source
12.3.8.2
MIRROR_DEST_MAC[5:0] - Mirror Destination MAC Address 0~5
CPU Address: h0700-0705 Accessed by CPU (R/W) DEST_MAC5 [47:40] (Default 00) DEST_MAC4 [39:32] (Default 00) DEST_MAC3 [31:24] (Default 00) DEST_MAC2 [23:16] (Default 00) DEST_MAC1 [15:8] (Default 00) DEST_MAC0 [7:0] (Default 00)
12.3.8.3
MIRROR_SRC _MAC[5:0] - Mirror Source MAC Address 0~5
CPU Address: h0706-070B Accessed by CPU (R/W) SRC_MAC5 [47:40] (Default 00) SRC_MAC4 [39:32] (Default 00) SRC_MAC3 [31:24] (Default 00) SRC_MAC2 [23:16] (Default 00) SRC_MAC1 [15:8] (Default 00) SRC_MAC0 [7:0] (Default 00)
102
Zarlink Semiconductor Inc.
ZL50407
12.3.8.4 RMII_MIRROR0 - RMII Mirror 0
Data Sheet
CPU Address: h0710 Accessed by CPU (R/W) Bits [2:0]: Bit [3]: Source port to be mirrored Mirror path 0: Receive 1: Transmit Destination port for mirrored traffic Mirror enable
Bits [6:4]: Bit [7]:
12.3.8.5
RMII_MIRROR1 - RMII Mirror 1
CPU Address: h0711 Accessed by CPU (R/W) Bits [2:0]: Bit [3]: Source port to be mirrored Mirror path 0: Receive 1: Transmit Destination port for mirrored traffic Mirror enable
Bits [6:4]: Bit [7]:
12.3.9 12.3.9.1
(Group 8 Address) Per Port QOS Control FCRn - Port 0~9 Flooding Control Register
IC Address: h04C+n; CPU Address: h0800+n (n = port number) Accessed by CPU and IC (R/W) Bits [3:0]: U2MR: Unicast to Multicast Rate. Units in terms of time base defined in bits [6:4]. This is used to limit the amount of flooding traffic from Port n. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 0) Time Base for Unicast to Multicast, Multicast and Broadcast rate control of Port n: (Default = 000) 000 = 100 us 001 = 200 us 010 = 400 us 011 = 800 us 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 12.8 ms Reserved
Bits [6:4]:
Bit [7]:
103
Zarlink Semiconductor Inc.
ZL50407
12.3.9.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control
Data Sheet
IC Address: h05E+n; CPU Address: h0820+n (n = port number) Accessed by CPU and IC (R/W) This broadcast and multicast rate defines for Port n, the number of packets allowed to be forwarded within a specified time. Once the packet rate is reached, packets will be dropped. To turn off the rate limit, program the field to 0. Time base is based on register FCR0 [6:4] Bits [3:0]: Bits [7:4]: Multicast Rate Control. Number of multicast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0). Broadcast Rate Control. Number of broadcast packets allowed within the time defined in bits 6 to 4 of the Flooding Control Register (FCRn). (Default 0)
12.3.9.3
PR100_n - Port 0~7 Reservation
IC Address: h06A+n; CPU Address: h0840+n (n = port number) Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.4
PR100_CPU - Port CPU Reservation
IC Address: h073; CPU Address: h0848 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. (Default 0x6)
12.3.9.5
PRG - Port GMAC Reservation
IC Address: h072; CPU Address: h0849 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. (Default 0x24)
12.3.9.6
PTH100_n - Port 0~7 Threshold
IC Address: h0C2+n; CPU Address: h0860+n (n = port number) Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x3)
12.3.9.7
PTH100_CPU - Port CPU Threshold
IC Address: h0CB; CPU Address: h0868 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x3)
104
Zarlink Semiconductor Inc.
ZL50407
12.3.9.8 PTHG - Port GMAC Threshold
Data Sheet
IC Address: h0CA; CPU Address: h0869 Accessed by CPU and IC (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x12)
12.3.9.9
QOSC00, QOSC01 - Classes Byte Limit port 0
IC Address: h078-079; CPU Address: h0880-0881 Accessed by CPU and IC (R/W) * * QOSC00 - Port 0 L1 threshold for queue 1 QOSC01 - Port 0 L2 threshold for queue 1
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.10
QOSC02, QOSC15 - Classes Byte Limit port 1-7
IC Address: h07A-087; CPU Address: h0882-088F Accessed by CPU and IC (R/W) Same as QOSC00, QOSC01 for ports 1-7
12.3.9.11
I 2C
QOSC16 - QOSC21 - Classes Byte Limit CPU port
Address: h088-08D; CPU Address: h0890-0895
Accessed by CPU and I2C (R/W): * * * * * * QOSC16 QOSC17 QOSC18 QOSC19 QOSC20 QOSC21 - - - - - - Port Port Port Port Port Port 8 8 8 8 8 8 (CPU) (CPU) (CPU) (CPU) (CPU) (CPU) L1 L2 L1 L2 L1 L2 threshold threshold threshold threshold threshold threshold for for for for for for queue queue queue queue queue queue 1 1 2 2 3 3
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.12
QOSC22 - QOSC27 - Classes Byte Limit GMAC port
IC Address: h08E-08F; CPU Address: h0896-089B Accessed by CPU and IC (R/W) * * * * * * QOSC22 QOSC23 QOSC24 QOSC25 QOSC26 QOSC27 - - - - - - Port Port Port Port Port Port 9 9 9 9 9 9 (uplink) (uplink) (uplink) (uplink) (uplink) (uplink) L1 L2 L1 L2 L1 L2 threshold threshold threshold threshold threshold threshold for for for for for for queue queue queue queue queue queue 1 1 2 2 3 3
105
Zarlink Semiconductor Inc.
ZL50407
Data Sheet
Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop) or Y% (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED.
12.3.9.13
QOSC28 - QOSC31 - Classes WFQ Credit For GMAC
CPU Address: h089C-089F Accessed by CPU (R/W) * * * * QOSC28 QOSC29 QOSC30 QOSC31 - - - - CREDIT_C00 CREDIT_C01 CREDIT_C02 CREDIT_C03
Bits [5:0] in QOSC28 through QOSC31 represents one set of WFQ parameters for GMAC port. The granularity of the numbers is 1, and their sum must be 64. QOSC31 corresponds to queue 3, that is the highest priority, and QOSC27 corresponds to queue 0. Default scheduling method will be strict priority across all queues. Only when the bit [7] is set, the queue will be scheduled as WFQ. The credit number also works as shaper credit if bit [6] is set. A queue with shaper enabled will be scheduled by strict priority when the token is available. The shaper setting override the WFQ (bit [7]) setting. Bits [5:0]: Bit [6]: Class scheduling credit Traffic Shaper Enable 0: Disable 1: Enable Enable WFQ Scheduling 0: Strict Priority 1: WFQ
Bit [7]:
12.3.9.14
QOSC36 - QOSC39 - Shaper Control Port GMAC
CPU Address: h08A4-08A7 Accessed by CPU (R/W) * * * * QOSC36 QOSC37 QOSC38 QOSC39 - - - - TOKEN_LIMIT_C00 TOKEN_LIMIT_C01 TOKEN_LIMIT_C02 TOKEN_LIMIT_C03
QOSC36 through QOSC39 represents one set of token limit on the shaper of GMAC port. The granularity of the numbers is 64 bytes. The shaper is implemented as leaky bucket and the limit here works as bucket size. Since the hardware implementation can keep negative number, the limit can be as small as one and still can transmit oversized frame, as long as one byte token is available.
12.3.10
(Group E Address) System Diagnostic
NOTE: Device Manufacturing test registers.
106
Zarlink Semiconductor Inc.
ZL50407
12.3.10.1 DTSRL - Test Output Selection
Data Sheet
CPU Address: h0E00 Accessed by CPU (R/W) Test group selection for testout[7:0].
12.3.10.2
DTSRM - Test Output Selection
CPU Address: h0E01 Accessed by CPU (R/W) Test group selection for testout[15:8].
12.3.10.3
TESTOUT0, TESTOUT1 - Testmux Output [7:0], [15:8]
CPU Address: h0E02-0E03 Accessed by CPU (RO)
12.3.10.4
MASK0-MASK4 - Timeout Reset Mask
CPU Address: h0E10-E14 Accessed by CPU (R/W) Disable timeout reset on selected state machine status. See Programming Timeout Reset application note, ZLAN-41, for more information.
12.3.10.5
BOOTSTRAP0 - BOOTSTRAP3
CPU Address: h0E80-E83 Accessed by CPU (RO) 31 BT3 Bits [15:0]: 23 BT2 15 BT1 BT0 0
Bootstrap value from TSTOUT[15:0]: Bit [6:0]: TSTOUT[6:0] Bit [8:7]: Invert of TSTOUT[8:7] Bit [9]: TSTOUT[11] Bit [10]: TSTOUT[9] Bit [11]: TSTOUT[10] Bit [14:12]: TSTOUT[14:12] Bit [15]: Always 0 Bootstrap value from M[7:0]_TXEN Bit [16]: M0_TXEN Bit [17]: M1_TXEN ... Bit [23]: M7_TXEN Bootstrap value from M9_TXEN, M9_TXER
Bits [23:16]:
Bits [25:24]:
107
Zarlink Semiconductor Inc.
ZL50407
Bits [31:26]: Reserved
Data Sheet
12.3.10.6
PRTFSMST0~9
CPU Address: h0E90+n Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6] Bit [7]: TX FSM NOT idle for 5 sec TX FIFO control NOT idle for 5 sec RX SFD detection NOT idle for 5 sec RXINF NOT idle for 5 sec PTCTL NOT idle for 5 sec Reserved LHB frame detected LHB receiving timeout
12.3.10.7
PRTQOSST0-PRTQOSST7
CPU Address: h0EA0+n Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Source port reservation low No source port buffer left Unicast congestion detected on best effort (P0) queue Reserved High priority queue reach L1 WRED level High priority queue reach L2 WRED level Low priority MC queue full High priority MC queue full
12.3.10.8
PRTQOSST8A, PRTQOSST8B (CPU port)
CPU Address: h0EA8 - 0EA9 Accessed by CPU (RO) 15 PQSTB PQSTA 0
108
Zarlink Semiconductor Inc.
ZL50407
Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Bit [8]: Bit [9]: Bit [10]: Bit [11]: Bit [12]: Bit [13]: Bits [15:14]: Source port reservation low No source port buffer left Unicast congestion detected on best effort (P0) queue Reserved priority queue 1 reach L1 WRED level priority queue 1 reach L2 WRED level priority queue 2 reach L1 WRED level priority queue 2 reach L2 WRED level priority queue 3 reach L1 WRED level priority queue 3 reach L2 WRED level priority 0 MC queue full priority 1 MC queue full priority 2 MC queue full Priority 3 MC queue full Reserved
Data Sheet
12.3.10.9
PRTQOSST9A, PRTQOSST9B (GMAC port)
CPU Address: h0EAA - 0EAB Accessed by CPU (RO) 15 PQSTB Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Bit [8]: Bit [9]: Bit [10]: Bit [11]: Bit [12]: Source port reservation low No source port buffer left Unicast congestion detected on best effort (P0) queue Reserved Priority queue 1 reach L1 WRED level Priority queue 1 reach L2 WRED level Priority queue 2 reach L1 WRED level Priority queue 2 reach L2 WRED level Priority queue 3 reach L1 WRED level Priority queue 3 reach L2 WRED level Priority 0 MC queue full Priority 1 MC queue full Priority 2 MC queue full PQSTA 0
109
Zarlink Semiconductor Inc.
ZL50407
Bit [13]: Bits [15:14]: Priority 3 MC queue full Reserved
Data Sheet
12.3.10.10
CLASSQOSST
CPU Address: h0EAC Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bits [7:4]: No share buffer No class 1 buffer No class 2 buffer No class 3 buffer Reserved
12.3.10.11
PRTINTCTR
CPU Address: h0EAD Accessed by CPU (R/W) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bit [4]: Bit [5]: Bit [6]: Bit [7]: Interrupt when source buffer low Interrupt when no source buffer Interrupt when UC congest Interrupt when L1 WRED level Interrupt when L2 WRED level Interrupt when MC queue full Interrupt when LHB timeout Interrupt when no class buffer
12.3.10.12
QMCTRL0~9
CPU Address: h0EB0+n Accessed by CPU (R/W) Bit [0]: Bit [1]: Bits [4:2]: Bit [5]: Bit [6]: Bit [7]: Suspend port scheduling (no departure) Reset queue Reserved Force out MAC control frame Force out XOFF flow control frame Force out XON flow control frame
110
Zarlink Semiconductor Inc.
ZL50407
12.3.10.13 QCTRL
Data Sheet
CPU Address: h0EBA Accessed by CPU (R/W) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bits [7:4]: Stop QM FSM at idle Stop MCQ FSM at idle Stop new granule grant to any source Stop release granule from any source Reserved
12.3.10.14
BMBISTR0, BMBISTR1
CPU Address: h0EBB - 0EBC Accessed by CPU (RO)
12.3.10.15
BMControl
CPU Address: h0EBD Accessed by CPU (R/W) Bits [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Reserved
Bits [7:4]:
111
Zarlink Semiconductor Inc.
ZL50407
12.3.10.16 BUFF_RST
Data Sheet
CPU Address: h0EC0 Accessed by CPU (R/W) Bits [3:0] Assign a value that the pool to be reset 0: port 0 pool 1: port 1 pool 2: port 2 pool 3: port 3 pool 4: port 4 pool 5: port 5 pool 6: port 6 pool 7: port 7 pool 8: port GMAC pool 9: shared pool 10: class 1 pool 11: class 2 pool 12: class 3 pool 13: multicast pool 14: cpu pool 15: reserved If this bit is 1, then all the pools are assigned Set 1 to reset the pools that are assigned Reserved
Bit [4] Bit [5] Bits [7:6]
If CPU wants to reset pools again, CPU has to clear bit 5 and then set bit 5. Note: Before CPU doing so, CPU should set QCTRL (CPU Address EBA) bit 2 and bit 3 to one. After reset the pools, CPU shall reprogram free granule link list (CPU address EC1, EC2, EC3, EC4, EC5, EC6). Then clear QCTRL (EBA).
12.3.10.17
FCB_HEAD_PTR0, FCB_HEAD_PTR1
CPU address: h0EC1 Accessed by CPU (R/W) Bits [7:0] CPU address: h0EC2 Accessed by CPU (R/W) Bits [6:0] Bit [7] Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Set 1 to write Fcb_head_ptr[7:0]. The head pointer of free granule link that CPU assigns.
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
112
Zarlink Semiconductor Inc.
ZL50407
12.3.10.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1
Data Sheet
CPU address: h0EC3 Accessed by CPU (R/W) Bits [7:0] CPU address: h0EC4 Accessed by CPU (R/W) Bits [6:0] Bit [7] Fcb_tail_ptr[14:8]. The tail pointer of free granule link that CPU assigns. Set 1 to write Fcb_tail_ptr[7:0]. The tail pointer of free granule link that CPU assigns.
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15.
12.3.10.19
FCB_NUM0, FCB_NUM1
CPU address: h0EC5 Accessed by CPU (R/W) Bits [7:0] CPU address: h0EC6 Accessed by CPU (R/W) Bits [6:0] Bit [7] Fcb_number[14:8]. The total number of granules that CPU assigns. Set 1 to write Fcb_number[7:0]. The total number of granules that CPU assigns.
If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. Note: There are two ways to reprogram the free granules. 1. CPU links all the granules: CPU writes memory directly, at last write head pointer (address EC1, EC2), tail pointer (address EC3, EC4) and granule number (address EC5, EC6). 2. CPU tells Buffer Manager to link: CPU clear head pointer (address EC1, EC2), clear tail pointer (address EC3, EC4), then write granule number that tells Buffer Manager to link (address EC5, EC6).
12.3.10.20
BM_RLSFF_CTRL
CPU address: h0EC7 Accessed by CPU (R/W) Bit [0] Bits [7:1] Read BM release FIFO. Reserved
The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from 0 to 1.
113
Zarlink Semiconductor Inc.
ZL50407
12.3.10.21 BM_RSLFF_INFO[5:0]
Data Sheet
CPU address: h0EC8 Accessed by CPU (RO) Bits [7:0] CPU address: h0EC9 Accessed by CPU (RO) Bits [6:0] Bit [7] CPU address: h0ECA Accessed by CPU (RO) Bits [7:0] CPU address: h0ECB Accessed by CPU (RO) Bits [5:0] Bits [7:6] CPU address: h0ECC Accessed by CPU (RO) Bits [4:0] Bit [5] Bits [7:6] CPU address: h0ECD Accessed by CPU (RO) Bits [1:0] Bits [3:2] Bit [4] Bits [7:5] Rls_src_port[3:2] Class[1:0] This release request is from QM directly. Entries count in release FIFO, 0 means FIFO is empty Rls_count[6:2] If 1, then It is multicast packet. Rls_src_port[1:0[ Rls_tail_ptr[14:9] Rls_count[1:0] Rls_tail_ptr[8:1] Rls_head_ptr[14:8]. Rls_tail_ptr[0] Rls_head_ptr[7:0].
114
Zarlink Semiconductor Inc.
ZL50407
12.3.11 12.3.11.1 (Group F Address) CPU Access Group GCR - Global Control Register
Data Sheet
CPU Address: h0F00 Accessed by CPU (R/W) Bit [0]: Store configuration (Default = 0) Write `1' followed by `0' to store configuration into external EEPROM Bit [1]: Store configuration and reset (Default = 0) Write `1' to store configuration into external EEPROM and reset chip Bit [2]: Start BIST (Default = 0) Write `1' followed by `0' to start the device's built-in self-test. The result is found in the DCR register. Bit [3]: Soft Reset (Default = 0) Write `1' to reset chip Bit [4]: Initialization Completed (Default = 0) This bit is reserved in unmanaged mode. In managed mode, the CPU writes this bit with `1' to indicate initialization is completed and ready to forward packets. The `0' to '1' transition will toggle TSTOUT[2] from low to high. Bits [7:5]: Reserved
115
Zarlink Semiconductor Inc.
ZL50407
12.3.11.2 DCR - Device Status and Signature Register
Data Sheet
CPU Address: h0F01 Accessed by CPU (RO) Bit [0]: Bit [1]: Bit [2]: Bit [3]: Bits [5:4]: Bits [7:6]: 1: Busy writing configuration to IC 0: Not busy (not writing configuration to IC) 1: Busy reading configuration from IC 0: Not busy (not reading configuration from IC) 1: BIST in progress 0: BIST not running 1: RAM Error 0: RAM OK Device Signature 11: ZL50407 device Revision 00: Initial Silicon 01: Second Silicon
12.3.11.3
DCR1 - Device Status Register 1
CPU Address: h0F02 Accessed by CPU (RO) Bits [6:0] Bit [7] Reserved Chip initialization completed
12.3.11.4
DPST - Device Port Status Register
CPU Address: h0F03 Accessed by CPU (R/W) Bits [4:0]: Read back index register. This is used for selecting what to read back from DTST. (Default 00) - 5'b00000 - Port 0 Operating mode and Negotiation status - 5'b00001 - Port 1 Operating mode and Negotiation status - 5'b00010 - Port 2 Operating mode and Negotiation status - 5'b00011 - Port 3 Operating mode and Negotiation status - 5'b00100 - Port 4 Operating mode and Negotiation status - 5'b00101 - Port 5 Operating mode and Negotiation status - 5'b00110 - Port 6 Operating mode and Negotiation status - 5'b00111 - Port 7 Operating mode and Negotiation status - 5'b01000 - Port CPU Operating mode and Negotiation status - 5'b01001 - Port GMAC Operating mode and Negotiation status Reserved
Bits [7:5]:
116
Zarlink Semiconductor Inc.
ZL50407
12.3.11.5 DTST - Data read back register
Data Sheet
CPU Address: h0F04 Accessed by CPU (RO) This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control Application Note, ZLAN-37. Bit [0] Flow control enable 1: Flow control 0: No flow control Full duplex port 1: Full duplex 0: Half duplex Fast Ethernet port (if bit [5] not set) 1: FE Port Link is down 1: Link down 0: Link up Auto negotiation disabled 1: Disable 0: Enable Gigabit Ethernet port 1: GE Port Reserved Module detected (for hot swap purpose) 0: No module 1: Module detected Note: If Module Detect feature is disabled (bootstrap TSTOUT[9]='0'), this bit will always be `1'.
Bit [1]
Bit [2] Bit [3]
Bit [4]
Bit [5] Bit [6] Bit [7]
12.3.11.6
DA - Dead or Alive Register
CPU Address: h0FFF Accessed by CPU (RO) Always return 8'h DA. Indicate the CPU interface or serial port connection is good. Bits [7:0] Always return DA
117
Zarlink Semiconductor Inc.
ZL50407 13.0
13.1
Data Sheet
Characteristics and Timing
Absolute Maximum Ratings
-65C to +150C -40C to +85C +125C +2.95 V to +3.65 V +1.60 V to +2.00 V -0.5 V to (VCC + 2.5 V) -0.5 V to (VDD + 0.3 V)
Storage Temperature Operating Temperature Maximum Junction Temperature Supply Voltage VCC with Respect to VSS Supply Voltage VDD with Respect to VSS Voltage on 5 V Tolerant Input Pins Voltage on Other Pins
Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied.
13.2
DC Electrical Characteristics
TAMBIENT = -40 C to +85 C
VCC = 3.3 V +/- 10% VDD = 1.8 V +/- 5%
118
Zarlink Semiconductor Inc.
ZL50407
13.3 Recommended Operating Conditions
Data Sheet
Symbol fosc ICC IDD Pwr VOH VOL VIH VIL IIL
Parameter Description Min. Frequency of Operation (SCLK) VCC (3.3V) Supply Current @ 100 MHz VDD (1.8V) Supply Current @ 100 MHz Power @ SCLK = 100MHz Output High Voltage (CMOS) Output Low Voltage (CMOS) Input High Voltage (TTL 5 V tolerant) Input Low Voltage (TTL 5 V tolerant) Input Leakage Current (0.1 V < VIN < VCC) (all pins except those with internal pull-up/pull-down resistors) Output Leakage Current (0.1 V < VOUT < VCC) Input Capacitance Output Capacitance I/O Capacitance Thermal resistance with 0 air flow Thermal resistance with 1 m/s air flow Thermal resistance with 2 m/s air flow Thermal resistance between junction and case 2.0 2.4 0.4 VCC + 2.0 0.8 10 Typ. 100 Max. 100 105 350 0.98 Unit MHz mA mA W V V V V A
IOL CIN COUT CI/O ja ja ja jc
10 5 5 7 24.3 20.0 18.1 4.6
A pF pF pF C/W C/W C/W C/W
119
Zarlink Semiconductor Inc.
ZL50407
13.4 13.4.1 AC Characteristics and Timing Typical Reset & Bootstrap Timing Diagram
Data Sheet
RESIN#
RESETOUT# Tri-Stated
R1 R3
Bootstrap Pins Outputs Inputs
R2
Outputs
Figure 11 - Typical Reset & Bootstrap Timing Diagram
Symbol R1 R2 R3
Parameter Delay until RESETOUT# is tri-stated Bootstrap stabilization RESETOUT# assertion
Min.
Typ. 10 ns
Refer to Figure 11 RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising edge of RESIN#
1 s
10 s 2 ms
Table 12 - Reset Timing
120
Zarlink Semiconductor Inc.
ZL50407
13.4.2 Synchronous Serial Interface (SSI)
Data Sheet
STROBE Datain D1 D2
D4 D1 D2
D5
Figure 12 - SSI Setup & Hold Timing
STROBE
D3-max D3-min
Dataout
Figure 13 - SSI Output Delay Timing
Symbol D1 D2
Parameter DATAIN setup time DATAIN hold time
Min. (ns) 20 3 s 20
Max. (ns)
Notes
Debounce on Debounce off 50 Debounce on CL = 100 pf Debounce off CL = 100 pf
D3* D3** D4
DATAOUT output delay time 1
STROBE low time
5 s 50
Debounce on Debounce off Debounce on Debounce off 100 kHz 10 MHz Debounce on Debounce off
D5
STROBE high time
5 s 50
STROBE frequency of operation
* Open Drain Output. Low to High transition is controlled by external pullup resistor. ** Totem Pole Output.
121
Zarlink Semiconductor Inc.
ZL50407
13.4.3 EEPROM Inter-Integrated Circuit (IC)
SCL
S1 S2
Data Sheet
SDA
Figure 14 - IC Setup & Hold Timing
SCL
S3-max S3-min
SDA
Figure 15 - IC Output Delay Timing
SCL=50 KHz Symbol S1 S2 S3* Parameter Min. (ns) SDA input setup time SDA input hold time SDA output delay time 20 1 4 s 6 s CL = 30 pf Max. (ns) Notes
* Open Drain Output. Low to High transition is controlled by external pullup resistor.
122
Zarlink Semiconductor Inc.
ZL50407
13.4.4 Reduced Media Independent Interface (RMII)
M_CLK
M6-max M6-min
Data Sheet
Mn_TXEN
M7-max M7-min
Mn_TXD[1:0]
Figure 16 - RMII Transmit Timing
M_CLK
M2
Mn_RXD
M3
Mn_CRS_DV
M4 M5
Figure 17 - RMII Receive Timing
M_CLK=50 MHz Symbol M2 M3 M4 M5 M6 M7 Parameter Min. (ns) M[7:0]_RXD[1:0] Input Setup Time M[7:0]_RXD[1:0] Input Hold Time M[7:0]_CRS_DV Input Setup Time M[7:0]_CRS_DV Input Hold Time M[7:0]_TXEN Output Delay Time M[7:0]_TXD[1:0] Output Delay Time 4 2 4 3 2 2 11 11 CL = 20 pF CL = 20 pF Max. (ns) Notes
123
Zarlink Semiconductor Inc.
ZL50407
13.4.5 Media Independent Interface (MII)
Mn_TXCLK
MM6-max MM6-min
Data Sheet
Mn_TXEN
MM7-max MM7-min
Mn _TXD[3:0]
Figure 18 - MII Transmit Timing
Mn_RXCLK
MM2
Mn_RXD[3:0] Mn_CRS_DV
MM4 MM 3 MM 5
Figure 19 - MII Receive Timing
25 MHz Symbol Parameter Min. (ns) Max. (ns) Notes
MM2 MM3 MM4 MM5 MM6 MM7
Mn_RXD[3:0] Input Setup Time Mn_RXD[3:0] Input Hold Time Mn_CRS_DV Input Setup Time Mn_CRS_DV Input Hold Time Mn_TXEN Output Delay Time Mn_TXD[3:0] Output Delay Time
4 2 4 2 2 2 14 14 CL = 20 pF CL = 20 pF
124
Zarlink Semiconductor Inc.
ZL50407
13.4.6 Reverse Media Independent Interface (RvMII)
Mn_TXCLK
RM6-max RM6-min
Data Sheet
Mn_TXEN
RM7-max RM7-min
Mn _TXD[3:0]
Figure 20 - RvMII Transmit Timing
Mn_RXCLK
RM2
Mn_RXD[3:0]
RM3
Mn_CRS_DV
RM4 RM5
Figure 21 - RvMII Receive Timing
25 MHz Symbol Parameter Min. (ns) Max. (ns) Notes
RM2 RM3 RM4 RM5 RM6* RM7*
Mn_RXD[3:0] Input Setup Time Mn_RXD[3:0] Input Hold Time Mn_CRS_DV Input Setup Time Mn_CRS_DV Input Hold Time Mn_TXEN Output Delay Time Mn_TXD[3:0] Output Delay Time
4 2 4 2 2 2 14 14 CL = 20 pF CL = 20 pF
* May need to add external delay depending on other MAC device's min. hold time.
125
Zarlink Semiconductor Inc.
ZL50407
13.4.7 General Purpose Serial Interface (GPSI)
Mn_TXCLK
SM6-max SM6-min
Data Sheet
Mn_TXEN
SM7-max SM7-min
Mn_TXD
Figure 22 - GPSI Transmit Timing
Mn_RXCLK
SM2
Mn_RXD
SM3
Mn_CRS_DV
SM4 SM5
Figure 23 - GPSI Receive Timing
10 MHz Symbol Parameter Min. (ns) Max. (ns) Notes
SM2 SM3 SM4 SM5 SM6 SM7
M[7:0]_RXD Input Setup Time M[7:0]_RXD Input Hold Time M[7:0]_CRS_DV Input Setup Time M[7:0]_CRS_DV Input Hold Time M[7:0]_TXEN Output Delay Time M[7:0]_TXD Output Delay Time
4 2 4 2 2 2 14 14 CL = 20 pF CL = 20 pF
126
Zarlink Semiconductor Inc.
ZL50407
13.4.8 Reverse General Purpose Serial Interface (RvGPSI)
Mn_TXCLK
RS6-max RS6-min
Data Sheet
Mn_TXEN
RS7-max RS7-min
Mn_TXD
Figure 24 - RvGPSI Transmit Timing
Mn_RXCLK
RS2
Mn_RXD
RS3
Mn_CRS_DV
RS4 RS5
Figure 25 - RvGPSI Receive Timing
10 MHz Symbol Parameter Min. (ns) Max. (ns) Notes
RS2 RS3 RS4 RS5 RS6* RS7*
M[7:0]_RXD Input Setup Time M[7:0]_RXD Input Hold Time M[7:0]_CRS_DV Input Setup Time M[7:0]_CRS_DV Input Hold Time M[7:0]_TXEN Output Delay Time M[7:0]_TXD Output Delay Time
4 2 4 2 2 2 14 14 CL = 20 pF CL = 20 pF
* May need to add external delay depending on other MAC device's min. hold time.
127
Zarlink Semiconductor Inc.
ZL50407
13.4.9 Gigabit Media Independent Interface (GMII)
M9_TXCLK
G12-max G12-min
Data Sheet
M9_TXD [7:0]
G13-max G13-min
M9_TXEN
G14-max G14-min
M9_TXER
Figure 26 - GMII Transmit Timing
M 9_RXCLK M9_RXCLK
G1 G2
M9_RXD[7:0] M 9_RXD[7:0]
G3 G4
M 9_RXDV M9_RXDV
G5 G6
M9_RXER M 9_RXER
G7 G8
M9_RX_CRS M 9_RX_CRS
Figure 27 - GMII Receive Timing
128
Zarlink Semiconductor Inc.
ZL50407
125 Mhz Symbol Parameter Min. (ns) Max. (ns)
Data Sheet
Notes
G1 G2 G3 G4 G5 G6 G7 G8 G12 G13 G14
M9_RXD[7:0] Input Setup Times M9_RXD[7:0] Input Hold Times M9_RXDV Input Setup Times M9_RXDV Input Hold Times M9_RXER Input Setup Times M9_RXER Input Hold Times M9_CRS Input Setup Times M9_CRS Input Hold Times M9_TXD[7:0] Output Delay Times M9_TXEN Output Delay Times M9_TXER Output Delay Times
2 0.5 2 0.5 2 0.5 2 0.5 1 1 1 5 5.5 5 CL = 20 pf CL = 20 pf CL = 20 pf
129
Zarlink Semiconductor Inc.
ZL50407
13.4.10 MII Management Data Interface (MDIO/MDC)
MDC
MD1 MD2
Data Sheet
MDIO
Figure 28 - MDIO Setup & Hold Timing
MDC
MD3-max MD3-min
MDIO
Figure 29 - MDIO Output Delay Timing
MDC=500 KHz Symbol Parameter Min. (ns) Max. (ns) Notes
MD1 MD2 MD3
MDIO input setup time MDIO input hold time MDIO output delay time
10 2 1 20 CL = 50 pf
130
Zarlink Semiconductor Inc.
ZL50407
13.4.11 JTAG (IEEE 1149.1-2001)
Data Sheet
TCK
TMS, TDI
J1
J2
J3-max
TDO
J3-min
Figure 30 - JTAG Timing Diagram
Symbol
Parameter
Min.
Typ.
Max.
Units
Refer to Figure 30
TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 J2 J3 TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid
0 20 10 20 3 7 0
10
50
MHz ns ns
-
ns ns ns
TRST is an asynchronous signal
15
ns
131
Zarlink Semiconductor Inc.
TOP VIEW
BOTTOM VIEW
MIN MAX Dimension 1.40 A A1 0.30 0.50 0.53 REF A2 D 16.90 17.10 16.90 17.10 E 0.40 0.60 b 1.00 e N 208 Conforms to JEDEC MO-192
b
SIDE VIEW
c Zarlink Semiconductor 2002 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 213730 14Nov02
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of ZL50407

	To Download ZL50407 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .